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bq76925

www.ti.com

SLUSAM9B –JULY 2011– REVISED DECEMBER 2011

Host Controlled Analog Front End for 3-Series to 6-Series Cell Li-Ion/Li-Polymer Battery

Protection and Gas Gauging Applications

Check for Samples: bq76925

FEATURES

DESCRIPTION

The bq76925 Host controlled analog front end (AFE)

• Analog Interface for Host cell Measurement

is part of a complete pack monitoring, balancing and

– Cell Input MUX, Level Shifter, and Scaler

protection system for 3-, 4-, 5-, or 6-series cell Li-Ion

– 1.5-/ 3.0-V Low-Drift, Calibrated Reference

and Li-Polymer batteries. The bq76925 allows a Host

Allows Accurate Analog to Digital

controller to easily monitor individual cell voltages,

pack current and temperature. This information may

Conversions

be used by the Host to determine unsafe or faulty

• Analog Interface for Host Current

operating conditions such as overvoltage,

Measurement

undervoltage, over-temperature and overcurrent, as

– Variable Gain Current Sense Amplifier

well as cell imbalance, state of charge and state of

Capable of Operation with 1-mΩ Sense

health conditions.

Resistor

Cell input voltages are level-shifted, multiplexed,

• Switchable Thermistor Bias output for Host

scaled, and output for measurement by a Host ADC.

Temperature Measurements

A low-drift calibrated reference voltage is provided on

a dedicated pin to enable accurate measurements.

• Overcurrent Comparator with Dynamically

Adjustable Threshold

The voltage across an external sense resistor is

– Alerts Host to Potential Overcurrent Faults

amplified and output to a Host ADC for both charge

and discharge current measurements. Two gain

– May be used to Wake up Host on Load

settings enable operation with a variety of sense

Connect

resistor values over a wide range of pack currents.

• Integrated Cell Balancing FETs

To enable temperature measurements by the Host,

– Individual Host Control

the AFE provides a separate output pin for biasing an

– 50 mA per-cell Balancing Current

external thermistor network. This output can be

switched on and off under Host control to minimize

• Supports Cell Sense-line Open Wire Detection

power consumption.

• Integrated 3.3-V Regulator for Powering

Micro-controller and/or LEDs

The bq76925 includes a comparator with a

dynamically selectable threshold for monitoring

• I

C Interface for Host Communications

current. The comparator result is driven through an

– Optional Packet CRC for Robust Operation

open-drain output to alert the host when the threshold

• Supply Voltage Range From 4.2 to 26.4 V

is exceeded. This feature can be used to wake up the

Host on connection of the load, or to alert the Host to

• Low Power Consumption

a potential fault condition.

– 40 µA Typical in Normal Mode

The bq76925 integrates cell balancing FETs that are

– 1.5 µA Maximum in Sleep Mode

fully controlled by the Host. The balancing current is

• 20-pin TSSOP or 24-pin QFN Package

set by external resistors up to a maximum value of 50

mA. These same FETs may be utilized in conjunction

APPLICATIONS

with cell voltage measurements to detect an open

wire on a cell sense-line.

• Primary Protection in Li-Ion Battery Packs

– Cordless Power Tools

The Host communicates with the AFE via an I

interface. A packet CRC may optionally be used to

– Light Electric Vehicles (E-Bike, Scooter,

ensure robust operation. The device may be put into

etc.)

a low-current sleep mode via the I

C interface and

– UPS Systems

awakened by pulling up the ALERT pin.

– Medical Equipment

– Portable Test Equipment

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Host Controlled Analog Front End for 3-Series to 6-Series Cell Li-Ion/Li-Polymer Battery Protection and Gas Gauging Applications Check for Samples: bq76925 FEATURES DESCRIPTION • The bq76925 Host controlled analog front end (AFE) is part of a complete pack monitoring, balancing and protection system for 3-, 4-, 5-, or 6-series cell Li-Ion and Li-Polymer batteries.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com FUNCTIONAL BLOCK DIAGRAM PACK+ Bypass FET (optional) Hold-up circuit (optional) RBAT 3.3 V µC / LED Supply RVCTL DBAT BAT VCTL VREG ZBAT CBAT POR V3P3 VC6 CV3P3 RIN + - CIN Cell Select VC5 I2C Bal Select SCL RIN + I2C Interface VC4 RIN Cell MUX + - CIN Level Shift VC3 RIN Balance Control + - CIN NTC Bias Switch Thresh Select CIN VCOUT Select EE - SDA REGS Ref Select 1.5 / 3.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) RANGE (2) VBAT Supply voltage range Input voltage range VI MIN MAX UNITS BAT –0.3 36 V Cell input differential, VCn to VCn+1, n = 0 to 5 –0.3 9 Cell input, VCn, n = 1 to 6 –0.3 (6 × n) BAT to VC6 differential –10 10 –3 3 –3 3 VC0 (3) SENSEP, SENSEN Output voltage range VO SCL, SDA –0.3 6 VCOUT, VIOUT, VREF –0.3 3.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS (1) MIN Supply voltage range MAX UNIT BAT 4.2 TYP 26.4 V Cell input differential, VCn to VCn+1, n = 0 to 5 1.4 4.4 V 4.4 × n V 8 V –125 375 mV 0 5.5 V 5.5 V 0 26.4 V 0 V3P3 + 0.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS BAT = 4.2 to 26.4 V, VCn = 1.4 to 4.4, TA = –25°C to 85°C Typical values stated where TA = 25°C and BAT= 21.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com 3.3 V Voltage Regulator PARAMETER TEST CONDITION MIN TYP MAX UNIT 26.4 V 3.4 V 3.3 V VOLTAGE REGULATOR VCTL Regulator control voltage VV3P3 Regulator output IREG V3P3 output current ISC (1) (2) Measured at VCTL, V3P3 regulating 3.3 Measured at V3P3, IREG = 0 to 4 mA, BAT = 4.2 to 26.4 V 3.2 V3P3 short circuit current limit V3P3 = 0.0 V 10.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Current Sense Amplifier PARAMETER GVIOUT VIIN TEST CONDITION Current sense amplifier gain Measured from SENSEN, SENSEP to VIOUT Current sense amp input range Measured from SENSEN, SENSEP to VSS Current sense amp output range Measured at VIOUT Zero current output Measured at VIOUT SENSEP = SENSEN VIOUT ∆VIOUT Current amplifier accuracy IVIOUT VIOUT output current (1) MIN TYP MAX UNIT –125 375 mV REF_SEL = 0 0.25 1.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com I2C Compatible Interface DC PARAMETERS MIN VIL Input Low Logic Threshold VIH Input High Logic Threshold VOL Output Low Logic Drive VOH Output High Logic Drive (Not applicable due to open-drain outputs) ILKG I2C Pin Leakage TYP MAX UNIT 0.6 V 2.8 V IOL = 1 mA 0.20 IOL = 2.5 mA V 0.40 N/A Pin = 5.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com OPERATIONAL OVERVIEW INTRODUCTION The bq76925 Host controlled analog front end (AFE) is part of a complete pack monitoring, balancing and protection system for 3 to 6 series cell Lithium batteries. The bq76925 allows a Host controller to easily monitor individual cell voltages, pack current and temperature.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com POWER MODES Power On Reset (POR) When initially powering up the bq76925, the voltage on the BAT pin must exceed VPOR (4.7 V max) before the device will turn on. Following this, the device will remain operational as long as the voltage on BAT remains above VSHUT (3.6 V max). If the BAT voltage falls below VSHUT the device will shut down. Recovery from shutdown occurs when BAT rises back above the VPOR threshold and is equivalent to a POR.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com The SLEEP_DIS bit in the POWER_CTL register acts as an override to the sleep function. When SLEEP_DIS is set to ‘1’, writing the SLEEP bit has no effect (i.e. sleep mode cannot be entered). If SLEEP_DIS is set after sleep mode has been entered, the device will immediately exit sleep mode. This scenario can arise if SLEEP_DIS is set after SLEEP is set, but before V3P3 has discharged below a valid operating voltage.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Host ADC Calibration All analog to digital converters have inherent gain and offset errors which adversely affect measurement accuracy. Some microcontrollers may be characterized by the manufacturer and shipped with ADC gain and offset information stored on-chip. It is also possible for such characterization to be done by the end-user on loose devices prior to PCB assembly, or as a part of the assembled PCB test.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com The actual cell voltage (VCn) is calculated from the measured voltage (VCOUT) as shown in the following equations: ADC Count VCOUT = × VREFNOMINAL Full Scale Count VCn = VCOUT ´ GCV REF + OCVCOUT G VCO UT × (1 + GC VCOUT ) (1) spacer spacer GCVCOUT = éë(VCn_GC_4 << 4 ) + VCn_GAIN_CORR ùû ´ 0.001, OCVCOUT = ëé(VCn_OC_4 << 4 ) + VCn_OFFSET_CORR ûù ´ 0.001, GCVREF = (1 + éë(VREF_GC_4 << 4 ) + VREF_GAIN_CORR ùû ´ 0.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com PACK+ RBAT DBAT Z BAT BAT VCTL VREG CBAT V3P3 CV3P3 VC6 + - bq76925 Figure 6. Sources of Voltage Drop Affecting the BAT Pin The top cell amplifier (VC6 – VC5) is designed to measure an input voltage down to 1.4 V with a difference between the BAT and VC6 pin up to 1.2 V (i.e. BAT can be 1.2 V lower than VC6). However, in applications with fewer than 6 cells, the upper cell inputs are typically shorted to the top cell input.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com The Host sets GVIOUT by writing the I_GAIN bit in the CONFIG_1 register. The available gains of 4 and 8 enable operation with a variety of sense resistor values over a broad range of pack currents. The gain may be changed at any time allowing for dynamic range and resolution adjustment. The input and output ranges of the amplifier are determined by the value of the REF_SEL bit in the CONFIG_2 register. These values are shown in Table 2.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Cell Balancing and Open Cell Detection The bq76925 integrates cell balancing FETs that are individually controlled by the Host. The balancing method is resistive bleed balancing, where the balancing current is set by the external cell input resistors. The maximum allowed balancing current is 50 mA per cell. The Host may activate one or more cell balancing FETs by writing the BAL_n bits in the BAL_CTL register.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Bus Write Command to bq76925 The Host writes to the registers of the bq76925 as shown in Figure 7. The bq76925 acknowledges each received byte by pulling the SDA line low during the acknowledge period. The Host may optionally send a CRC after the Data byte as shown. The CRC for write commands is enabled by writing the CRC_EN bit in the CONFIG_2 register.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com VCOUT_SEL CELL_SEL VCOUT 01 010 VC3 01 011 VC4 01 100 VC5 01 101 VC6 01 110 VTEMP,INT 01 111 Hi-Z BAL_CTL Address Name Type 0x02 BAL_CTL R/W Defaults: D7 D6 0 0 D5 D4 D3 D2 D1 D0 BAL_6 BAL_5 BAL_4 BAL_3 BAL_2 BAL_1 0 0 0 0 0 0 BAL_n: Balance control for cell n. When set, turns on balancing transistor for cell n. Setting of two adjacent balance controls is not permitted.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com I_GAIN: Current amplifier gain. Sets the nominal gain of the current amplifier as follows. I_GAIN Current amp gain 0 4 1 8 CONFIG_2 Address Name Type D7 0x04 CONFIG_2 R/W CRC_EN Defaults: D6 D5 D4 D3 D2 D1 D0 REF_SEL 0 0 0 0 0 0 0 0 CRC_EN: CRC enable. Enables CRC comparison on write. When ‘1’, CRC is enabled. CRC on read is always enabled but is optional for Host. REF_SEL: Reference voltage selection.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com VREF_GAIN_CORR: Lower 4 bits of gain correction factor for reference output. The complete gain correction factor is obtained by concatenating this value with the most significant bit VREF_GC_4, which is stored in the VREF_CAL_EXT register. The final value is a 5-bit signed 2’s complement number in the range -16 to +15 with a value of 0.1% per lsb. See description of usage in OPERATIONAL OVERVIEW.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com VC4_CAL Address Name Type 0x14 VC4_CAL EEPROM D7 D6 D5 D4 D3 D2 VC4_OFFSET_CORR D1 D0 VC4_GAIN_CORR VC4_OFFSET_CORR: Lower 4 bits of offset correction factor for cell 4 translation. The complete offset correction factor is obtained by concatenating this value with the most significant bit VC4_OC_4, which is stored in the VC_CAL_EXT_2 register.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com VC_CAL_EXT_2 Address Name Type D7 D6 D5 D4 D3 D2 D1 D0 0x18 VC_CAL_EXT_2 EEPROM VC3_OC_4 VC3_GC_4 VC4_OC_4 VC4_GC_4 VC5_OC_4 VC5_GC_4 VC6_OC_4 VC6_GC4 VC3_OC_4: Most significant bit of offset correction factor for cell 3 translation. See VC3_CAL register description for details. VC3_GC_4: Most significant bit of gain correction factor for cell 3 translation. See VC3_CAL register description for details.
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Changes from Original (July 2011) to Revision A • Page Changed literature number to Rev A for ProductMix release ...............................................................................................
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bq76925 SLUSAM9B – JULY 2011 – REVISED DECEMBER 2011 www.ti.com Changes from Revision A (July 2011) to Revision B Page • Added 24-pin QFN (RGE) Package to Production Data ....................................................................................................... 2 • Added 24-pin QFN (RGE) Package to Production Data .......................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ76925PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1 BQ76925RGER VQFN RGE 24 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2 BQ76925RGET VQFN RGE 24 250 180.0 12.4 4.25 4.25 1.15 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ76925PWR TSSOP PW 20 2000 367.0 367.0 38.0 BQ76925RGER VQFN RGE 24 3000 367.0 367.0 35.0 BQ76925RGET VQFN RGE 24 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.