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bq76PL536A-Q1

www.ti.com

SLUSAM3 –MAY 2011

3 to 6 Series Cell Lithium-Ion Battery Monitor and Secondary Protection IC for EV and

HEV Applications

Check for Samples: bq76PL536A-Q1

FEATURES

DESCRIPTION

The bq76PL536A-Q1 is a stackable three to six

• 3 to 6 Series Cell Support, All Chemistries

series cell lithium-ion battery pack protector and

• Hot-Pluggable

analog front end (AFE) that incorporates a precision

• High-Speed SPI for Data Communications

analog-to-digital converter (ADC); independent cell

• Stackable Vertical Interface

voltage and temperature protection; cell balancing,

and a precision 5-V regulator to power user circuitry.

• No Isolation Components Required Between

ICs

The bq76PL536A-Q1 integrates a voltage translation

• Qualified for Automotive Applications

and precision analog-to-digital converter system to

• Temperature Range –40°C to 105°C

measure battery cell voltages with high accuracy and

speed.

• High-Accuracy Analog-to-Digital Converter

(ADC):

The bq76PL536A-Q1 provides full protection

– ±1 mV Typical Accuracy

(secondary protection) for overvoltage, undervoltage,

and overtemperature conditions. When safety

– 14-Bit Resolution, 6-µs Conversion Time

thresholds are exceeded, the bq76PL536A-Q1 sets

– Nine ADC Inputs: 6 Cell Voltages, 1 Six-Cell

the FAULT output. No external components are

Brick Voltage, 2 Temperatures, 1

needed to configure or enable the protection features.

General-Purpose Input

– Dedicated Pins for Synchronizing

Cell voltage and temperature protection functions are

Measurements

independent of the ADC system. Programmable

protection thresholds and detection delay times are

• Configuration Data Stored in ECC-OTP

stored in Error Check/Correct (ECC) OTP EPROM,

Registers

which increases the flexibility and reliability of the

• Built-In Comparators (Secondary Protector)

battery management system.

for:

The bq76PL536A-Q1 is intended to be used with a

– Over- and Undervoltage Protection

host controller to maximize the functionality of the

– Overtemperature Protection

battery management system. However, the protection

– Programmable Thresholds and Delay Times

functions do not require a host controller.

– Dedicated Fault Signals

The bq76PL536A-Q1 can be stacked vertically to

• Cell Balancing Control Outputs With Safety

monitor up to 192 cells without additional isolation

Timeout

components between ICs. A high-speed serial

– Balance Current Set by External

peripheral interface (SPI) bus operates between each

Components

bq76PL536A-Q1 to provide reliable communications

• Supply Voltage Range from 6 V to 30 V

through a high-voltage battery cell stack.

Continuous and 36 V Peak

• Low Power:

– Typical 12-µA Sleep, 45-µA Idle

• Integrated Precision 5-V, 3-mA LDO

APPLICATIONS

• Electric and Hybrid Electric Vehicles

• E-Bike and E-Scooter

• Uninterruptible Power Systems (UPS)

• Large-Format Battery Systems

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (60 pages)

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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The host microcontroller controls cell balancing of individual cells by setting registers (via SPI) which control the appropriate CBx outputs.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com PIN NAME NO. TYPE (1) DESCRIPTION BAT2 64 P Power-supply voltage, connect to most-positive cell +, tie to BAT1 on PCB CB1 12 O Cell-balance control output CB2 10 O Cell-balance control output CB3 8 O Cell-balance control output CB4 6 O Cell-balance control output CB5 4 O Cell-balance control output CB6 2 O Cell-balance control output CONV_H 36 I Host-to-device interface – initiates a synchronous conversion.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 PIN NAME NO. www.ti.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com ORDERING INFORMATION (1) TA PACKAGE PART NO. –40°C To 105°C 64 TQFP PowerPAD package bq76PL536ATPAPQ1 (1) The bq76PL536ATPAPQ1 can be ordered in tape and reel as bq76PL536ATPAPRQ1 (quantity 1000) or bq76PL536ATPAPTQ1 (quantity 250). LDOD LDO-A LDO-D VBAT LDOA REG50 AUX FUNCTIONAL BLOCK DIAGRAM bq76PL536 CONV_N TS2+ OT1 1.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) Supply voltage range, VMAX BAT1, BAT2 (1) (2) –0.3 to 2 0 to 36 TS1+, TS1–, TS2+, TS2– –0.3 to 6 GPAI –0.3 to 6 GPIO –0.3 to VREG50 + 0.3 DRDY_N, SDO_N, FAULT_N, ALERT_N VBAT – 1 to VBAT + 2 CONV_S, SDI_S, SCLK_S, CS_S –2 to 1 CONV_N, SDI_N, SCLK_N, CS_N –0.3 to 36 V –0.3 to 5 –0.3 to VREG50 + 0.3 GPIO CB1…CB6 (CBREF = 0x00) –0.3 to 36 REG50, AUX –0.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS SUPPLY CURRENT Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com HOST INTERFACE Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40°C to 105°C and VBAT = 7.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com VCn (Cell) Inputs Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted), FUNCTION_CONFIG[]=01xxxx00b for all test conditions (6-µs conversion time selected). PARAMETER TEST CONDITIONS Input voltage range (1) VIN MIN VCn – VCn–1, where n = 1 to 6 (2) TYP 6 VRES Voltage resolution –10°C ≤ TA ≤ 50°C, 1.2 V < VIN < 4.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com TSn Measurement (continued) Typical values stated where TA = 25°C and VBAT = 20V, Min/Max values stated where TA = –40˚C to 105°C and VBAT = 7.2V to 27V (unless otherwise noted), FUNCTION_CONFIG[]=01xxxx00b for all Test Conditions PARAMETER VRES TEST CONDITION MIN 14 bits, REG50 = 5 V, (Resolution ≈ VREG50/215) Voltage resolution, (2) (2) 0.25 V ≤ VIN ≤ 2.4 V TYP –0.7% ±0.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com UNDERVOLTAGE LOCKOUT (UVLO) and POWER-ON RESET (POR) Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 105°C and VBAT = 7.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com BATTERY PROTECTION DELAY TIMES Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 105°C and VBAT = 7.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com AC TIMING CHARACTERISTICS SPI DATA INTERFACE Typical values stated where TA = 25°C and VBAT = 20 V, Min/Max values stated where TA = –40˚C to 105°C and VBAT = 7.2 V to 27 V (unless otherwise noted) PARAMETER TEST CONDITION MIN TYP MAX UNIT 10 250 1000 kHz fSCLK SCLK frequency (1) SCLKDC SCLK_H duty cycle, t(HIGH) / t(SCLK) or t(LOW) / t(SCLK) tCS,LEAD CS_H lead time, CS_H low to clock 50 SCLK/2 tCS,LAG CS_H lag time.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com 3 to 6 Series Cell Configuration When fewer than 6 cells are used, the most-positive cell voltage of the series string should be connected to the BAT1/BAT2 pins, through the RC input network shown in the Reference Schematic section. Unused VCx inputs should be connected to the next VCx input down until an input connected to a cell is reached – i.e., in a four cell stack, VC6 connects to VC5, which connects to VC4.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com The GPAI measurement can be configured to use one of two references via FUNCTION_CONFIG[GPAI_REF]. Either the internal bandgap (VREF) or REG50 can be selected. When REG50 is selected, the ADC returns a ratio of the voltage at the inputs and REG50, removing the need for compensation of the REG50 voltage accuracy or drift when used as a source to excite the sensor.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com REG50 RTH 47 nF RT RB = 0.4 (RTH@40C – RTH@90C) TS+ RT = RTH@ 40C – 2RTH @90C – RB RB TS– Figure 5. Thermistor Connection Converting TSn Result to Voltage (Ratio) To convert the returned TSn measurement value to a ratio, RTS = VTS:REG50, the following formulas are used. The setting FUNCTION_CONFIG[] = 0100 xxxxb is assumed. Note that the offset and gain correction are slightly different for each channel.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Hardware Start A single interface pin (CONV_H) is used for conversion-start control by the host. A conversion cycle is started by a hardware signal when CONV_H is transitioned low-to-high by the host. The host should hold this state until the conversion cycle is complete to avoid erroneous edges causing a conversion start when the present conversion is not complete.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com MEASUREMENT General-purpose analog input ADC_CONTROL GPAI = 1 Conversion Time Control The ADC conversion time is fixed at approximately 6 µs per converted channel, plus 6 µs overhead at the start of the conversion. Total conversion time (µs) is approximately 6 × num_channels + 6. Automatic vs Manual Control The ADC_CONTROL[ADC_ON] bit controls powering up the ADC section and the main bandgap reference.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Cell Overvoltage Fault Detection (COV) When the voltage across a cell exceeds the programmed COV threshold for a period of time greater than set in the COV timer (COVT), the COV_FAULT[] flag for that cell is set. The bits in COV_FAULT[] are then ORed into the FAULT[COV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H) pin also to be asserted.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com FAULT[CUV] flag, which is then ORed into the DEVICE_STATUS[FAULT] flag, which causes the FAULT_S (_H) pin also to be asserted. The CUV flag is latched unless CUVT is programmed to 0, in which case the flag follows the fault condition. Care should be taken when using this setting to avoid chatter of the fault status. To reset the FAULT flag, first remove the source of the fault (i.e.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Table 1. Overtemperature Trip Setpoints OT THRESHOLDS (1) CONFIG_OT TNOM °C VTS RATIO SET VTS RATIO CLEAR VSET (1) VCLEAR (1) 0 Disabled Disabled Disabled Disabled Disabled 1 40 0.2000 0.1766 1.000 0.883 2 45 0.2244 0.2000 1.122 1.000 3 50 0.2488 0.2270 1.244 1.135 4 55 0.2712 0.2498 1.356 1.249 5 60 0.2956 0.2750 1.478 1.375 6 65 0.3156 0.2956 1.578 1.478 7 70 0.3356 0.3162 1.678 1.581 8 75 0.3556 0.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Table 2.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com modified by the host from 1 to 0, or by expiration of the timing period. The timing begins counting the programmed period from start each time the CB_CTRL[] register is programmed from a zero to a non-zero value in the lower six bits.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Auxiliary Power Output (AUX) The bq76PL536A-Q1 provides an approximately 1-mA auxiliary power output that is controlled via IO_CONTROL[AUX]. This output is taken directly from REG50. The current drawn from this pin must be included in the REG50 current-limit budget by the designer. Undervoltage Lockout and Power-On Reset The device incorporates two comparators to detect low VBAT conditions.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com GPIO The bq76PL536A-Q1 includes a general-purpose input/output pin controlled by the IO_CONTROL[GPIO_OUT] bit. The state of this bit is reflected on the pin. To use the pin as an input, program GPIO_OUT to a 1, and then read the IO_CONTROL[GPIO_IN] bit. A pullup (10 kΩ–1 MΩ, typ.) is required on this pin if used as an input.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com The pins of the base IC (only) in a stack should have the SCLK_H and SDI_H pins terminated with pullups to minimize current draw of the part if the host ever enters a state where the pins are not driven, i.e., held in the high-impedance state by the host. In non-base devices, the _H pins are forced to be all outputs driven low when the HSEL pin is high. In non-base devices, all _H pins should remain unconnected.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Packet Formats Data Read Packet When the bq76PL536A-Q1 is selected (CS_S [CS_H for first device] is active and the bq76PL536A-Q1 has been addressed) and read request has been initiated, then the data is transmitted on the SDO_S pin to the SDO_N pin of the next device down the stack. This continues to the first device in the stack, where the data in from the SDO_N pin is transmitted to the host via the SDO_H pin.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Write Packet 0 Device Address R/W 1 Reg Address Reg Data CS Assertion CRC Figure 12. WRITE Packet Detail Broadcast Writes The bq76PL536A-Q1 supports broadcasting single register writes to all devices. A write to device address 0x3f is recognized by all devices on the bus with a valid address, and permits efficient simultaneous configuration of all registers in the stack of devices.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com The data packet can be periodically expanded to accommodate temperature and GPAI readings as well as device status as needed by changing the REGISTER_FIRST offset and LENGTH values. Device Addressing Each individual device in the series stack requires an address to allow it to be communicated with. Each bq76PL536A-Q1 has a CS_S and CS_N that are used in assigning addresses.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Once the address is written, the ADDRESS_CONTROL[AR] bit is set which is copied to the DEVICE_STATUS[AR] and also ALERT_S if ALERT_N is also de-asserted. This allows the CS_N pin to follow (asserted) the CS_S pin assertions. The process of addressing can now be repeated as device ‘n’ has a new address and device n+1 has the default address of 0x00, and can be changed to its correct address in the stack.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Read / Write, Initialized From EPROM (Group3) These registers control the device configuration and functionality. The contents of the registers are initialized from EPROM-stored constants as a result of POR, RESET command, or the RELOAD_SHADOW command. This feature ensures that the secondary protector portion of the device (COV, CUV, OT) is fully functional after any reset, without host CPU involvement.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com When a double-bit (uncorrectable) error is found, DEVICE_STATUS[ALERT] is set, the ALERT_S (ALERT_H for bottom stack device) line is activated, and the ALERT_STATUS[] register returns the ECC_ERR and/or I_FAULT bit = 1(true). The device may return erroneous measurement data, and/or fail to detect COV, CUV, or OT faults in this state. EPROM bits are shipped from the factory set to 0, and must be programmed to the 1 state as required. Table 3.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Table 3.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com REGISTER DETAILS DEVICE_STATUS REGISTER (0x00) 7 AR 6 FAULT 5 ALERT 4 – 3 ECC_COR 2 UVLO 1 CBT 0 DRDY The STATUS register provides information about the current state of the bq76PL536A-Q1. [7] (ADDR_RQST) This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address. This bit is a copy of in the ADDRESS_CONTROL[AR] bit.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com GPAI (0x01, 0x02) 15 GPAI[15] 7 GPAI [7] 14 GPAI [14] 6 GPAI [6] 13 GPAI [13] 5 GPAI [5] 12 GPAI [12] 4 GPAI [4] 11 GPAI [11] 3 GPAI [3] 10 GPAI [10] 2 GPAI [2] 9 GPAI [9] 1 GPAI [1] 8 GPAI [8] 0 GPAI [0] 9 VCELLn[9] 1 VCELLn[1] 8 VCELLn[8] 0 VCELLn[0] The GPAI register reports the ADC measurement of GPAI+/GPAI– in units of LSBs. Bits 15–8 are returned at address 0x01, bits 7–0 at address 0x02.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com [6] (PARITY): This bit is used to validate the contents of the protected Group3 registers. 0 = Group3 protected register(s) contents are valid. 1 = Group3 protected register(s) contents are invalid. Group3 registers should be refreshed from OTP or directly written from the host. [5] (ECC_ERR): This bit is used to validate the OTP register blocks.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com 1 = The internal consistency check has failed self-test. The host should attempt to reset the device, see the RESET section. If the fault persists, the failure should be considered uncorrectable. [4] (FORCE): This bit asserts the FAULT signal. It can be used to verify correct operation and connectivity of the FAULT line as a part of system self-test. 0 = Deassert FAULT (default) 1 = Assert the FAULT signal.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com The PRESULT_A register holds the parity result bits for the first eight Group3 protected registers. PARITY_H REGISTER (0x25) (PRESULT_B (R/O)) 7 0 6 0 5 0 4 0 3 USER4 2 USER3 1 USER2 0 USER1 The PRESULT_B register holds the parity result bits for the second eight Group3 protected registers.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com IO_CONTROL REGISTER (0x31) 7 AUX 6 GIPI_OUT 5 GPIO_IN 4 0 3 0 2 SLEEP 1 TS2 0 TS1 The IO_CONTROL register controls some features of the bq76PL536A-Q1 external I/O pins. [7] (AUX): Controls the state of the AUX output pin, which is internally connected to REG50. 0 = Open 1 = Connected to REG50 [6] (GPIO_OUT): Controls the state of the open-drain GPIO output pin; the pin should be programmed to 1 to use the GPIO pin as an input.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com CB_TIME REGISTER (0x33) 7 CBT[7] 6 – 5 CBT[5] 4 CBT[4] 3 CBT[3] 2 CBT[2] 1 CBT[1] 0 CBT[0] The CB_TIME register sets the maximum high (active) time for the cell balance outputs from 0 seconds to 63 minutes. When set to 0, no balancing can occur – balancing is effectively disabled. [7] Controls minutes/seconds counting resolution. 0 = Seconds (default) 1 = Minutes [5..0] Sets the time duration as scaled by CBT.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com ADDRESS_CONTROL REGISTER (0x3b) 7 AR 6 0 5 ADDR[5] 4 ADDR[4] 3 ADDR[3] 2 ADDR[2] 1 ADDR[1] 0 ADDR[0] The ADDRESS_CONTROL register allows the host to assign an address to the bq76PL536A-Q1 for communication. The default for this register is 0x00 at RESET. [7] (ADDR_RQST): This bit is written to indicate that the ADDR[0]…[5] bits have been written to the correct address.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com FUNCTION_CONFIG REGISTER (0x40) 7 0 6 0 5 GPAI_REF 4 GPAI_SRC 3 CN[1] 2 CN[0] 1 – 0 0 The FUNCTION_CONFIG sets the default configuration for special features of the device. [5] (GPAI_REF): This bit sets the reference for the GPAI ADC measurement.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com CONFIG_COV REGISTER (0x42) 7 DISABLE 6 – 5 COV[5] 4 COV[4] 3 COV[3] 2 COV[2] 1 COV[1] 0 COV[0] The CONFIG_COV register determines cell overvoltage threshold voltage. [7] (DISABLE): Disables the overvoltage function when set 0 = Overvoltage function enabled 1 = Overvoltage function disabled [5..0] (COV[5]…[0]): Configuration bits with corresponding voltage threshold 0x00 = 2 V; each binary increment adds 50 mV until 0x3c = 5 V.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com CONFIG_CUVT REGISTER (0x45) 7 µs/ms 6 – 5 – 4 CUVD[4] 3 CUVD[3] 2 CUVD[2] 1 CUVD[1] 0 CUVD[0] The CONFIG_CUVT register determines cell overvoltage detection delay time. [7] (µs/ms): Determines the units of the delay time, microseconds or milliseconds 0 = Microseconds 1 = Milliseconds [4..0] CUVD: 0x01 = 100; each binary increment adds 100 until 0x1f = 3100.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com PROGRAMMING THE EPROM CONFIGURATION REGISTERS The bq76PL536A-Q1 has a block of OTP-EPROM that is used for configuring the operation of the bq76PL536A-Q1. Programming of the EPROM should take place during pack/system manufacturing. A 7-V (VPP) pulse is required on the PROG pin. The part uses an internal window comparator to check the voltage, and times the internal pulse delivered to the EPROM array.
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2-VSS C84 .001uf 50V CAP0603 7 TP5 6 5 4 3 3 4 5 6 CELL 10 + CELL 9 + CELL 8 + CELL 7 + 6 7 CELL 1 + CELL 1 - TP1 4 5 3 CELL 4 + CELL 3 + 2 CELL 5 + CELL 2 + 1 CELL 6 + P1 39502-1007_7-POS 1-VSS C51 .
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CELL 1 + 1-VSS [1] 1-CELL2 [1] 1-CELL1 CELL 2 + [1,2] [1] 1-CELL3 CELL 3 + CELL 1 - [1] 1-CELL5 [1] 1-CELL4 CELL 5 + [1] 1-CELL6 CELL 4 + CELL 6 + C9 0.1uf 50V CAP0603 C19 0.1uf 50V CAP0603 C27 0.1uf 50V CAP0603 C37 0.1uf 50V CAP0603 C42 0.1uf 50V CAP0603 C48 0.1uf 50V CAP0603 Q7 FDN359AN SOT-23 R9 47 RES2512 Q4 FDN359AN SOT-23 Z1 5.1 VDC 500mW Q2 SOD-123 FDN359AN SOT-23 Z3 5.1 VDC 500mW SOD-123 R24 47 RES2512 Z5 5.1 VDC 500mW Q6 SOD-123 FDN359AN SOT-23 R38 47 RES2512 Z7 5.
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[1,3] CELL 1 - 2-VSS [1] 2-CELL2 [1] 2-CELL1 [1] 2-CELL3 CELL 3 + CELL 2 + [1] 2-CELL4 CELL 1 + [1] 2-CELL5 CELL 5 + [1] 2-CELL6 CELL 4 + CELL 6 + Q14 FDN359AN SOT-23 Z14 5.1 VDC 500mW Q10 SOD-123 FDN359AN SOT-23 R98 47 RES2512 Q11 FDN359AN SOT-23 R104 47 RES2512 Z18 5.1 VDC 500mW Q13 SOD-123 FDN359AN SOT-23 R114 47 RES2512 Z20 5.1 VDC 500mW SOD-123 R121 47 RES2512 Z22 5.1 VDC 500mW Q15 SOD-123 FDN359AN SOT-23 Z16 5.1 VDC 500mW SOD-123 C54 0.1uf 50V CAP0603 C58 0.
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[1] 3-CELL1 [1,4] CELL 1 + CELL 1 - 3-VSS [1] 3-CELL2 CELL 2 + [1] 3-CELL4 [1] 3-CELL3 [1] 3-CELL5 CELL 5 + CELL 4 + CELL 3 + [1] 3-CELL6 CELL 6 + C86 0.1uf 50V CAP0603 C87 0.1uf 50V CAP0603 C94 0.1uf 50V CAP0603 C101 0.1uf 50V CAP0603 C109 0.1uf 50V CAP0603 R177 47 RES2512 Q21 FDN359AN SOT-23 Z27 5.1 VDC 500mW Q17 SOD-123 FDN359AN SOT-23 R155 47 RES2512 Z29 5.1 VDC 500mW Q18 SOD-123 FDN359AN SOT-23 R167 47 RES2512 Z31 5.1 VDC 500mW Q20 SOD-123 FDN359AN SOT-23 Z33 5.
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bq76PL536A-Q1 SLUSAM3 – MAY 2011 www.ti.com Changes and Enhancements From bq76PL536 • • • • • 52 Improved power management during CRC faults – Configuration bit IO_CONFIG[CRCNOFLT] (bit7) was added to disable CRC fault from asserting the FAULT pin. This feature is useful under very low-power operating conditions. ADC accuracy improvements – The conversion timing is now fixed at 6µs, offering improved accuracy over the original bq76PL536.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant BQ76PL536ATPAPRQ1 HTQFP PAP 64 1000 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 BQ76PL536ATPAPTQ1 HTQFP PAP 64 250 330.0 24.4 13.0 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) BQ76PL536ATPAPRQ1 HTQFP PAP 64 1000 367.0 367.0 45.0 BQ76PL536ATPAPTQ1 HTQFP PAP 64 250 367.0 367.0 45.
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