Datasheet

DRDY
FAULT
ALERT
SPI
PACK–
PACK+
HOST
INTERFACE
GPAI
GPIO
AUX
REG50
HO S T IN TE R FA C E
CONV
CBx (6)
CELL_1
CELL_6
••• CELL_2-5 •••
GPAI
GPIO
AUX
HO S T I N TE R FA C E
(n o t u s ed )
CBx (6)
bq76PL536A-Q1
CELL_1
CELL_6
••• CELL_2-5 •••
ALERT
FAULT
DRDY
SPI
SPI
(North)
CONV
CONTROL (North)
TO NEXT DEVICE
ALERT
FAULT
DRDY
SPI
SPI
(North)
CONV
CONTROL (North)
CONTROL (South)
SPI
(South)
South Interface
(not used on bottom device)
bq76PL536A-Q1
bq76PL536A-Q1
SLUSAM3 –MAY 2011 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
DESCRIPTION (CONTINUED)
The host microcontroller controls cell balancing of individual cells by setting registers (via SPI) which control the
appropriate CBx outputs. These outputs can be turned off via the same control, or automatically by the internal
programmable safety timer. The balancing bypass current is set via an external series resistor and FET.
TYPICAL IMPLEMENTATION
Figure 1. Simplified System Connection
PIN DETAILS
PIN FUNCTIONS
PIN
TYPE
(1)
DESCRIPTION
NAME NO.
AGND 15 AI Internal analog V
REF (–)
ALERT_H 38 O Host-to-device interface – ALERT condition detected in this or higher (North) device
ALERT_N 57 I Current-mode input indicating a system status change from the next-higher bq76PL536A-Q1
ALERT_S 23 OD Current-mode output indicating a system status change to the next lower bq76PL536A-Q1
AUX 31 O Switched 1-mA limited output from REG50
BAT1 63 P Power-supply voltage, connect to most-positive cell +, tie to BAT2 on PCB
(1) Key: I = digital input, AI = analog input, O = digital output, OD = open-drain output, T = 3-state output, P = power.
2 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated
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