Datasheet

bq76PL536A-Q1
SLUSAM3 –MAY 2011 www.ti.com
Table 1. Overtemperature Trip Setpoints
OT THRESHOLDS
CONFIG_OT T
NOM
°C V
TS
RATIO SET V
TS
RATIO CLEAR V
SET
(1)
V
CLEAR
(1)
0 Disabled Disabled Disabled Disabled Disabled
1 40 0.2000 0.1766 1.000 0.883
2 45 0.2244 0.2000 1.122 1.000
3 50 0.2488 0.2270 1.244 1.135
4 55 0.2712 0.2498 1.356 1.249
5 60 0.2956 0.2750 1.478 1.375
6 65 0.3156 0.2956 1.578 1.478
7 70 0.3356 0.3162 1.678 1.581
8 75 0.3556 0.3368 1.778 1.684
9 80 0.3712 0.3528 1.856 1.764
10 85 0.3866 0.3688 1.933 1.844
11 90 0.4000 0.3824 2.000 1.912
(1) Assumes REG50 = 5.000 V
Thermistor Power
To minimize power consumption, the thermistors are not powered ON by default. Two bits are provided in
IO_CONTROL[] to control powering the thermistors, TS1 and TS2. The TSn– input is only connected to VSS
when the corresponding bit is set. The user firmware must set these bits to 1 to enable both temperature
measurement and the secondary protector functions. When the thermistor functions are not in use, the bits may
be programmed to 0 to remove current through the thermistor circuits.
Thermistor Input Conditioning
A filter capacitor is recommended to minimize noise in to the ADC and protector. The designer should insure that
the filter capacitor has sufficient time to charge before reading the thermistors. The CONFIG_OTT[] value should
also be set to >5t, the time delay introduced by the RC network comprising C
F
, R
TH
, R
T
, and R
B
, to avoid false
triggering of the PROTECTOR function and ALERT signal when the TS1 and/or TS2 bits are set to 1 and the
inputs enabled.
On exit from the SLEEP state, the OT fault comparators are disabled for approximately 200 µs to allow internal
circuitry to stabilize and prevent false error-condition detection.
Fault and Alert Behavior
When the FAULT_N pin is asserted by the next higher bq76PL536A-Q1 in the stack, then the FAULT_S is also
asserted, thereby passing the signal down the array of stacked devices if they are present. FAULT_N should
always be connected to the FAULT_S of the next higher device in the stack. If no higher device exists, it should
be tied to V
BAT
of this bq76PL536A-Q1, either directly or via a pullup resistor ~10 kΩ to 1 MΩ. The FAULT_x pins
are active-high – current flows when asserted. The ALERT_x pins behave in a similar manner. If the FAULT_N
pin of the base device (HSEL = 0) becomes asserted, it asserts its FAULT_H signal to the host microcontroller.
This signal chain may be used to create an interrupt to the CPU, or drive other compatible logic or I/O directly.
Table 2. Fault Detection Summary
SIGNALING
FAULT DETECTION PIN
DEVICE_STATUS
X_STATUS BIT SET
BIT SET
HSEL = 1 HSEL = 0
EPROM double bit
ECC logic fault detected FAULT_S FAULT_H FAULT FAULT_STATUS[I_FAULT]
error
FORCE User set FORCE bit FAULT_S FAULT_H FAULT FAULT_STATUS[FORCE]
POR Power-on reset occurred FAULT_S FAULT_H FAULT FAULT_STATUS[POR]
22 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated
Product Folder Link(s): bq76PL536A-Q1