Datasheet

bq76PL536-Q1

SLUSAB1 –MAY 2011

www.ti.com

NOTE

If a conversion cycle is inadvertedly started while (ADCT[1:0] ≠ 0 <AND> ADC_ON = 0),

the device appears to lock up and stop working. To correct this behavior, send a device

RESET command (write 0xa5 to register 0x3c) followed by any customer-specific register

initialization. The RESET command also resets the device address to 0x00, making it

necessary to reassign addresses to all devices in the stack.

The bit may be turned on and left on, or dynamically manipulated at each conversion depending on user

firmware requirements.

TI recommends programming the OTP register to set the conversion rate permanently. This procedure is

described in the data sheet for the device. A typical value for FUNCTION_CONFIG[] register 0x40 is 0x50. See

the FUNCTION_CONFIG REGISTER (0x40) section for further details of the other bit functions.

Procedure:

OTP EPROM is Pre-programmed to 6 µs (0x40 = 0101 xx00b):

1. Prior to any conversion:

Write ADC_CONFIG[ADC_ON] = 1 (0x30 = 01xx xxxxb)

Note: The typical setting used to convert all inputs is ADC_CONTROL[] = 0111 1101b.

Alternate Method - Use Shadow RAM Feature (EPROM 0x40 Programmed Value is Don’t Care):

The shadow RAM feature allows temporarily overwriting EPROM contents. At RESET, Group3 RAM registers are

loaded from OTP EPROM. The device always uses the contents of the RAM register internally to control the

device. The RAM register may be subsequently overwritten with a new value to modify the device defaults

programmed in EPROM. The new value is valid until the next device RESET. This example assumes that all

inputs are converted.

1. Setup for 6-µs/ch conversion time:

Write SHDW_CTRL[] = 0x35 (register 0x3a = 0x35) to enable the write to FUNCTION_CONFIG[].

Immediately followed by:

Write FUNCTION_CONFIG[] = 0x50 (register 0x40 = 0x50)

2. Prior to any conversion:

Write ADC_CTRL[] = 0x7d (register 0x30 = 0x7d)

Wait >1 ms before converting after setting ADC_ON = 1 in the previous step.

3. Converting:

Conversions are now initiated normally, using the CONV_H pin or the CONVERT[CONV] register bit.

Note: Power may be significantly reduced by setting the bit ADC_ON = 0.

Secondary Protection

The bq76PL536-Q1 integrates dedicated overvoltage and undervoltage fault detection for each cell and two

overtemperature fault detection inputs for each device. The protection circuits use a separate band-gap reference

from the ADC system and operate independently. The protector also uses separate I/O pins from the main

communications bus, and therefore is capable of signaling faults in hardware without intervention from the host

CPU.

Protector Functionality

When a fault state is detected, the respective fault flag in the FAULT_STATUS[] or ALERT_STATUS[] registers

is set. All flags in the FAULT and ALERT registers are then ORed into the DEVICE_STATUS[] FAULT and

ALERT bits. The FAULT and ALERT bits in DEVICE_STATUS[] in turn cause the hardware FAULT_S or

ALERT_S pin to be set. The bits in DEVICE_STATUS[] and the hardware pins are latched until reset by the host

via SPI command, ensuring that the host CPU does not miss an event.