Datasheet

OUTPUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
5 Cells
OUTPUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
6 Cells
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
OUTPUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
7 Cells (Stacked)
bq77PL157A4225
SLUSA00B –MARCH 2010–REVISED APRIL 2012 www.ti.com
BATTERY CONNECTION DIAGRAMS
The following schematics indicate the cell connections for several battery configurations. Unused cell inputs
should be connected together on the most positive end of the cell stack. (VC1 is the most positive input.)
The PCKP and PCKN pins supply power to the output FET driver. PCKP is always connected to the most
positive cell input of the device. PCKN for a single device or the bottom device in a stack is connected to the
source terminal of the protection FET device. For an upper device in a stacked configuration, PCKN is connected
to GND.
NOTE
Not all connections shown. Diagrams are simplifications of full circuits and do not include
key constraints when stacking these parts.
10 Copyright © 2010–2012, Texas Instruments Incorporated