Datasheet

VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
OUTPUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
12 Cells (Stacked)
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
OUTPUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
10 Cells (Stacked)
OUTPUT
18 Cells (Stacked)
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
LVIN
LVO
CD
OUT
bq77PL157A4225
www.ti.com SLUSA00B –MARCH 2010–REVISED APRIL 2012
REDUCING TEST TIME
By controlling the CD pin, it is possible to reduce the time for functional test at PC board assembly:
To make a shorter overvoltage delay time, pull the CD pin over 1.2 V (typ) (MAX to VDD).
To recover from an overvoltage condition, pull the CD pin down to GND and set cell VCx < V
PROTECT
– V
TH
.
Copyright © 2010–2012, Texas Instruments Incorporated 11