Datasheet

LVO
VC1
VC2
VC3
VC4
VC5
VC6
LVIN
NC
CD
VDD
NC
OUT
GND PCKN
1
bq77PL157
Low-Side
CHGFET
2
3
4
5
6
16
15
14
13
12
11
7
8 9
10
PCKP
bq77PL157A4225
SLUSA00B –MARCH 2010–REVISED APRIL 2012 www.ti.com
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
ORDERING INFORMATION
V
PROTECT
DEVICE FEATURE CONFIGURATION PACKAGING FULL PART NAME
Tape and Reel bq77PL157APWR-4225
4.225 V bq77PL157A Recoverable Output
Tube bq77PL157APW-4225
DEVICE INFORMATION
PW PACKAGE
(TOP VIEW)
PIN FUNCTIONS
PIN NAME PIN NO. DESCRIPTION
CD 14 External capacitor to GND to set delay time
GND 8 Ground pin and negative end of cell stack
LVIN 16 Level-shift input (used for stacking, input is from next-higher part)
LVO 1 Level-shift output (used for stacking, route this output to next-lower part)
NC 11, 15 No connection
OUT 10 Output gate drive to external MOSFET
PCKN 9 Pack negative supply for OUT driver (connect to source of external MOSFET or GND if device not at
bottom of stack)
PCKP 12 Pack positive supply for OUT driver (connect to most positive cell input of device)
VC1 2 Sense voltage input for most positive cell
VC2 3 Sense voltage input for second most positive cell
VC3 4 Sense voltage input for third most positive cell
VC4 5 Sense voltage input for fourth most positive cell
VC5 6 Sense voltage input for fifth most positive cell
VC6 7 Sense voltage input for least positive cell
VDD 13 Power supply (via RC filter)
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