Datasheet

H
LVIN
1 .2 V
CD
2 .4 V
I
CHLV
I
DS2
I
DSLV
V
LVL
I
CH2
I
IN
I
IN
I
IN
I
IN
I
IN
I
IN
I
CC
VC1
VC2
VC3
VC4
VC5
VC6
VDD
GND
1
2
3
4
5
6
16
15
14
13
12
11
7
8 9
10
PCKP
bq77PL157A4225
SLUSA00B –MARCH 2010–REVISED APRIL 2012 www.ti.com
Figure 3. CD Charge Current and Discharge Current
Figure 4. I
CC
, I
IN
Measurement Test Setup
OPERATION AND TIMING OF PROTECTION OUTPUT
From Direct Cell Inputs
When any one of the cell voltages exceeds V
PROTECT
, an internal current source begins to charge capacitor C
CD
connected to the CD pin, which acts as a delay timer. If all cell voltages fall below V
PROTECT
before V
CD
reaches
V
CD,TH1
, the delay timer is reset and the OUT pin is not activated (i.e., no fault detected, output remains
unchanged). An internal switch clamps the CD pin to GND, discharges the capacitor C
CD
, and resets the full
delay time for the next occurring overvoltage event.
If any cell voltage exceeds V
PROTECT
long enough for the voltage at the CD pin (V
CD
) to reach V
CD,TH1
(1.2 V
typical), then the OUT and LVO pins are activated (i.e., fault detected, output changes state), thus interrupting
the circuit via the FET protection device. Once the output is activated, the CD pin is charged up to its maximum
value V
CD,TH2
(2.4 V typical).
6 Copyright © 2010–2012, Texas Instruments Incorporated