Datasheet

1.2V
V
PROTECT
V
PROTECT
- V
TH
Cell Voltage
OUT
CD
LVO
(VCn - VC(n-1),
VC6 – GND)
t
D
= (1.2V x C
D
) / I
CH1
bq77PL157A4225
SLUSA00B –MARCH 2010–REVISED APRIL 2012 www.ti.com
Figure 6. Timing for Overvoltage Sensing (Without Recovery Option – Permanent Latch)
From Level Shift Input
More than six cells can be monitored with multiple bq77PL157 devices by using the LVO and LVIN pins to
cascade or stack multiple parts. The LVO pin from the upper bq77PL157 is connected to the LVIN pin of the
lower bq77PL157. The OUT pin of the lowest bq77PL157 is used to control the activation element while the OUT
pins of the upper bq77PL157 devices are not used.
When the LVIN pin changes from a low to high level, an internal current source begins to charge capacitor C
CD
,
connected to the CD pin, quickly. If the voltage at the CD pin, V
CD
, reaches V
CD,TH1
(1.2 V typical), then the OUT
pin and the LVO pin are both activated. Once the output is activated, the CD pin continues to charge up to its
maximum value of V
CD,TH2
(2.4 V typical).
The delay time from LVIN to either LVO or OUT is minimized by quickly charging the CD pin and is
approximately 10 times faster than the delay time from an overvoltage fault at the direct cell inputs. When more
than two bq77PL157 devices are stacked, this delay time is additive.
The delay time per device can be calculated as follows:
t
DA
= (V
CD,TH1
× C
CD
) / I
CHLV
where IC
HLV
= CD charge current = 10 × I
CH1
= 2 µA (typical)
When the LVIN pin changes from a high to low level, an internal switch clamps the CD pin to GND, discharging
the capacitor C
CD
. The delay time (per part) can be calculated as follows.
t
DIA
= (V
CD,TH2
– V
CD,TH1
) × C
CD
/ I
DSLV
where I
DSLV
= CD discharge current = 90 µA (typical)
To find the total expected delay time from LVIN to OUT, a variable internal latency of approximately 4 - 12 ms
should be added.
Faults detected via LVIN have the highest priority and will interrupt the timing of all lower priority faults.
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