Datasheet

Register Set
bq77PL900
SLUS844B – JUNE 2008 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
The bq77PL900 has 12 addressable registers. These registers provide status, control, and configuration
information for the battery protection system.
Table 10. Register Descriptions
TEST
NAME ADDR MEMORY R/W DESCRIPTION
PIN
STATUS X 0x00 Read R Status register
Output pin control from system host-control mode and external pin
OUTPUT_CONTROL X 0x01 RAM R/W
status
STATE_CONTROL X 0x02 RAM R/W State control from system host and external pin status
FUNCTION_CONTROL X 0x03 RAM R/W Function control from system host and external pin status
CELL BALANCE X 0x04 RAM R/W Battery cell select for balance bypass
CELL _SEL X 0x05 RAM R/W Battery cell select for balance bypass and for analog output voltage
OV CFG X 0x06 EEPROM R/W
(1)
Overvoltage level and delay time register
UV LEVEL X 0x07 EEPROM R/W
(1)
Undervoltage level register
OCV & UV DELAY X 0x08 EEPROM R/W
(1)
Overload voltage level and undervoltage delay time register
OCDELAY X 0x09 EEPROM R/W
(1)
Overload delay time register
SCD CFG X 0x0a EEPROM R/W
(1)
Short-circuit in discharge current level and delay time register
EEPROM X 0x0b RAM R/W EEPROM read and write enable register
(1) Write and read data will be match after write EEPROM writing procedure.
Table 11. Register Map
NAME B7 B6 B5 B4 B3 B2 B1 B0
I
2
C ADDR
STATUS 0x00 CHG DSG VGOOD OVTEMP UV OV OCD SCD
OUTPUT_CONTROL 0x01 FS PFALT 0 0 GPOD CHG DSG LTCLR
STATE_CONTROL 0x02 IGAIN VGAIN 0 0 0 0 HOST SHDN
FUNCTION_CONTROL 0x03 CBAL10 CBAL9 TOUT BAT PACK IACAL IAEN VAEN
[Cell(9,10) balance register]
CELL_BALANCE 0x04 CBAL8 CBAL7 CBAL6 CBAL5 CBAL4 CBAL3 CBAL2 CBAL1
CELL_SEL 0x05 0 CAL2 CAL1 CAL0 CELL4 CELL3 CELL2 CELL1
OV_CFG 0x06 OVD2 OVD1 OVD0 OVH1 OVH0 OV2 OV1 OV0
UV_CFG 0x07 0 UVFET_DIS UVH1 UVH0 UV3 UV2 UV1 UV0
OCV & UV_DELAY 0x08 UVD3 UVD2 UVD1 UVD0 OCD3 OCD2 OCD1 OCD0
OCD_CFG 0x09 CBEN ZVC SOR OCDD4 OCDD3 OCDD2 OCDD1 OCDD0
SCD_CFG 0x0a SCDD3 SCDD2 SCDD1 SCDD0 SCD3 SCD2 SCD1 SCD0
Read-writing 0 1 1 0 0 0 1 0
EEPROM Writing (0x41) 0x0b 0 1 0 0 0 0 0 1
Reading (except above) 0 0 0 0 0 0 0 0
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