Datasheet

OV_CFG: Overvoltage Delay Time, Hysteresis, and Threshold Configuration Register
bq77PL900
SLUS844B – JUNE 2008 – REVISED JANUARY 2009 ...................................................................................................................................................... www.ti.com
CELL_SEL b6 – b4 (CAL2 – 0): These three bits determine the mode of the voltage monitor block.
CAL2 CAL1 CAL0 SELECTED MODE
0 0 0 Cell translation for selected cell (default), VOUT output depends on CELL4 – 1.
0 0 1 Monitor offset of differential amplifier (both inputs of differential amplifier are
connected to GND).
0 1 0 Monitor the scaled V
REF
(1)
value.
0 1 1 Monitor V
REF
(1)
directly.
1 0 0 Monitor the scaled 2.5-V value to the measured 2.5 V.
1 0 1 Monitor V
REF
– 0 V, through the sample-and-hold circuit.
(1)
1 1 0 Monitor 2.5 V – 0 V through the sample-and-hold circuit.
1 1 1 Monitor 2.5 V – 1.2 V through the sample-and-hold circuit.
(1) When VGAIN = 0, VREF = 0.975 V; when VGAIN = 1, VREF = 1.2 V.
CELL_SEL b7: These bits are not used and should be set to 0.
OV CFG REGISTER (0x06)
7 6 5 4 3 2 1 0
OVD2 OVD1 OVD0 OVH1 OVH0 OV2 OV1 OV0
The OV register determines cell overvoltage threshold, hysteresis voltage, and detection delay time.
OV_CFG b2 – b0 (OV2 – 0) configuration bits with corresponding voltage threshold with a default of 000.
Resolution is 50 mV.
0x00 4.15 V 0x02 4.25 V 0x04 4.35 V 0x06 4.45 V
0x01 4.2 V 0x03 4.3 V 0x05 4.4 V 0x07 4.5 V
OV_CFG b4 – b3 (OVH1 – 0) configuration bits with corresponding hysteresis voltage with a default of 00.
Resolution is 100 mV.
0x00 0.1 V 0x01 0.2 V 0x02 0.3 V 0x03 0 V
OV_CFG b7 – b5 (OVD2 – 0) configuration bits with corresponding delay time for overvoltage with a default of 000.
Resolution is 250 ms.
0x00 0.5 s 0x02 1 s 0x04 1.5 s 0x06 2 s
0x01 0.75 s 0x03 1.25 s 0x05 1.75 s 0x07 2.25 s
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