Datasheet
SCD_CFG: Short-Circuit in Discharge Configuration Register
EEPROM: EEPROM Write Enable and Configurati0n Register
Zero-Volt Charging
bq77PL900
SLUS844B – JUNE 2008 – REVISED JANUARY 2009 ......................................................................................................................................................
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SCD_CFG REGISTER (0x0a)
7 6 5 4 3 2 1 0
SCDD3 SCDD2 SCDD1 SCDD0 SCD3 SCD2 SCD1 SCD0
The SCD_CFG register determines the short-circuit voltage threshold and detection delay time.
SCD_CFG b3 – b0 (SCD3 – 0): These lower-nibble bits select the value of the short-circuit in discharge voltage
threshold with 0000 as the default, units in mV, and a resolution of 5 mV.
0x00 60 mV 0x04 80 mV 0x08 100 mV 0x0c 120 mV
0x01 65 mV 0x05 85 mV 0x09 105 mV 0x0d 125 mV
0x02 70 mV 0x06 90 mV 0x0a 110 mV 0x0e 130 mV
0x03 75 mV 0x07 95 mV 0x0b 115 mV 0x0f 135 mV
SCD_CFG b7-b4 (SCDD3-0): These upper nibble bits select the value of the short circuit in discharge delay time.
0000 is the default, units of µ s and a resolution of 60 µ s.
0x00 0 µ s 0x04 240 µ s 0x08 480 µ s 0x0c 720 µ s
0x01 60 µ s 0x05 300 µ s 0x09 540 µ s 0x0d 780 µ s
0x02 120 µ s 0x06 360 µ s 0x0a 600 µ s 0x0e 840 µ s
0x03 180 µ s 0x07 420 µ s 0x0b 660 µ s 0x0f 900 µ s
EEPROM REGISTER (0x0b)
7 6 5 4 3 2 1 0
EEPROM7 EEPROM6 EEPROM5 EEPROM4 EEPROM3 EEPROM2 EEPROM1 EEPROM0
EEPROM b7 – b0 (EEPROM7 – 0):
These bits enable data write to EEPROM(0x06-0x9a) with 0100 0001 (0x41).
Prewriting data is available by setting these bits with 0110 0010 (0x62).
Default is 0000 0000 (0x00).
In order to charge cells, the CHG FET must be turned on to create a current path. When the battery voltage
(V
BAT
) is low and the CHG is ON, the pack voltage (V
PACK
) is as low as the battery voltage. In cases where the
level is below the supply voltage for the bq77PL900 is too low to operate, there are two configurations to provide
the appropriate 0-V/precharge function.
Common FET mode does not require a dedicated 0-V/precharge FET. The CHG FET is ON. This method is
suitable for a charger that has a 0-V/precharge function. The second mode is to use a 0-V/precharge FET which
establishes a dedicated 0-V/precharge current path by using an additional open drain (GPOD output) for driving
an external FET (PCHG FET). This configuration sustains the PACK+ voltage level. Any type of charger can be
used with this configuration.
Table 13. 0-V Charge Summary
PROTECTION DEMANDED CHARGE
0-V CHARGE TYPE APPLICATION CIRCUIT
MODE FUNCTION
Host-control mode Common FET (1) Fast charge PMS = PACK
Precharge GPOD output not used
0-V/precharge FET (2) Fast charge PMS = GND
GPOD output: Drives 0-V charge FET (PCHG FET)
Stand-alone mode Common FET (1) Fast charge PMS = PACK
Precharge GPOD output not used
0-V/precharge FET (2) Fast charge PMS = GND
GPOD output: Drives 0-V charge FET (PCHG FET)
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