Datasheet

MOTOROLA CMOS LOGIC DATAMC14024B
100
The MC14024B is a 7–stage ripple counter with short propagation delays
and high maximum clock rates. The Reset input has standard noise
immunity, however the Clock input has increased noise immunity due to
Hysteresis. The output of each counter stage is buffered.
• Diode Protection on All Inputs
• Output Transitions Occur on the Falling Edge of the Clock Pulse
• Supply Voltage Range = 3.0 Vdc to 18 Vdc
• Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load Over the Rated Temperature Range
• Pin–for–Pin Replacement for CD4024B
MAXIMUM RATINGS* (Voltages Referenced to V
SS
)
Symbol Parameter Value Unit
V
DD
DC Supply Voltage – 0.5 to + 18.0 V
V
in
, V
out
Input or Output Voltage (DC or Transient) – 0.5 to V
DD
+ 0.5 V
l
in
, l
out
Input or Output Current (DC or Transient),
per Pin
± 10 mA
P
D
Power Dissipation, per Package† 500 mW
T
stg
Storage Temperature – 65 to + 150
C
T
L
Lead Temperature (8–Second Soldering) 260
C
* Maximum Ratings are those values beyond which damage to the device may occur.
†Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C
Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C
LOGIC DIAGRAM
CLOCK
RESET
2
1
12
Q1
11
Q2
4
Q6
3
Q7
Q3 = PIN 9
Q4 = PIN 6
Q5 = PIN 5
C Q
R Q
C Q
R Q
C Q
R Q
C Q
R Q
SEMICONDUCTOR TECHNICAL DATA
 Motorola, Inc. 1995
REV 3
1/94
L SUFFIX
CERAMIC
CASE 632
ORDERING INFORMATION
MC14XXXBCP Plastic
MC14XXXBCL Ceramic
MC14XXXBD SOIC
T
A
= – 55° to 125°C for all packages.
P SUFFIX
PLASTIC
CASE 646
D SUFFIX
SOIC
CASE 751A
11
12
13
14
8
9
105
4
3
2
1
7
6
NC
Q2
Q1
NC
V
DD
NC
Q3
Q6
Q7
RESET
CLOCK
V
SS
Q4
Q5
PIN ASSIGNMENT
V
DD
= PIN 14
V
SS
= PIN 7
NC = NO CONNECTION