Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Buffer SO 16

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

Data sheet acquired from Harris Semiconductor

SCHS046I

CD4049UB, CD4050B

CMOS Hex Buffer/Converters

The CD4049UB and CD4050B devices are inverting and

non-inverting hex buffers, respectively, and feature logic-

level conversion using only one supply voltage (V

). The

input-signal high level (V

) can exceed the V

supply

voltage when these devices are used for logic-level

conversions. These devices are intended for use as CMOS

to DTL/TTL converters and can drive directly two DTL/TTL

loads. (V

= 5V, V

≤ 0.4V, and I

≥ 3.3mA.)

The CD4049UB and CD4050B are designated as

replacements for CD4009UB and CD4010B, respectively.

Because the CD4049UB and CD4050B require only one

power supply, they are preferred over the CD4009UB and

CD4010B and should be used in place of the CD4009UB

and CD4010B in all inverter, current driver, or logic-level

conversion applications. In these applications the

CD4049UB and CD4050B are pin compatible with the

CD4009UB and CD4010B respectively, and can be

substituted for these devices in existing as well as in new

designs. Terminal No. 16 is not connected internally on the

CD4049UB or CD4050B, therefore, connection to this

terminal is of no consequence to circuit operation. For

applications not requiring high sink-current or voltage

conversion, the CD4069UB Hex Inverter is recommended.

Features

• CD4049UB Inverting

• CD4050B Non-Inverting

• High Sink Current for Driving 2 TTL Loads

• High-To-Low Level Logic Conversion

• 100% Tested for Quiescent Current at 20V

• Maximum Input Current of 1µA at 18V Over Full Package

Temperature Range; 100nA at 18V and 25

• 5V, 10V and 15V Parametric Ratings

Applications

• CMOS to DTL/TTL Hex Converter

• CMOS Current “Sink” or “Source” Driver

• CMOS High-To-Low Logic Level Converter

Pinouts

Ordering Information

PART NUMBER

TEMP.

RANGE (

C) PACKAGE

CD4049UBF3A -55 to 125 16 Ld CERDIP

CD4050BF3A -55 to 125 16 Ld CERDIP

CD4049UBD -55 to 125 16 Ld SOIC

CD4049UBDR -55 to 125 16 Ld SOIC

CD4049UBDT -55 to 125 16 Ld SOIC

CD4049UBDW -55 to 125 16 Ld SOIC

CD4049UBDWR -55 to 125 16 Ld SOIC

CD4049UBE -55 to 125 16 Ld PDIP

CD4049UBNSR -55 to 125 16 Ld SOP

CD4049UBPW -55 to 125 16 Ld TSSOP

CD4049UBPWR -55 to 125 16 Ld TSSOP

CD4050BD -55 to 125 16 Ld SOIC

CD4050BDR -55 to 125 16 Ld SOIC

CD4050UBDT -55 to 125 16 Ld SOIC

CD4050BDW -55 to 125 16 Ld SOIC

CD4050BDWR -55 to 125 16 Ld SOIC

CD4050BE -55 to 125 16 Ld PDIP

CD4050NSR -55 to 125 16 Ld SOP

CD4050BPW -55 to 125 16 Ld TSSOP

CD4050BPWR -55 to 125 16 Ld TSSOP

NOTE: When ordering, use the entire part number. The sufﬁx R denotes tape

and reel. The sufﬁx T denotes a small-quantity reel of 250.

CD4049UB (PDIP, CERDIP, SOIC, SOP, TSSOP)

TOP VIEW

CD4050B (PDIP, CERDIP, SOIC, SOP)

TOP VIEW

G = A

H =

I =

K =

J =

L =

G = A

H = B

I = C

K = E

J = D

L = F

August 1998 - Revised May 2004

[

/Title

(

CD40

9UB,

D405

Sub-

ect

(

CMO

Hex

uffer/

on-

erters)

Autho

()

Key-

ords

(

Harris

emi-

on-

uctor,

D400

etal

ate,

MOS

Summary of content (38 pages)

PAGE 1
CD4049UB, CD4050B August 1998 - Revised May 2004 Data sheet acquired from Harris Semiconductor SCHS046I CMOS Hex Buffer/Converters Applications The CD4049UB and CD4050B devices are inverting and non-inverting hex buffers, respectively, and feature logiclevel conversion using only one supply voltage (VCC). The input-signal high level (VIH) can exceed the VCC supply voltage when these devices are used for logic-level conversions.
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CD4049UB, CD4050B Functional Block Diagrams CD4049UB A B C D E F 3 2 5 4 7 6 9 10 11 12 14 15 VCC VSS CD4050B G=A A H=B B I=C C J=D D K=E E L=F F 1 3 2 5 4 7 6 9 10 11 12 14 15 VCC 8 VSS NC = 13 NC = 16 G=A H=B I=C J=D K=E L=F 1 8 NC = 13 NC = 16 Schematic Diagrams VCC VCC P OUT R IN P P N N R IN N VSS FIGURE 1A. SCHEMATIC DIAGRAM OF CD4049UB, 1 OF 6 IDENTICAL UNITS 2 OUT VSS FIGURE 1B.
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CD4049UB, CD4050B Absolute Maximum Ratings Thermal Information Supply Voltage (V+ to V-). . . . . . . . . . . . . . . . . . . . . . . -0.5V to 20V DC Input Current, Any One Input. . . . . . . . . . . . . . . . . . . . . . ±10mA Package Thermal Impedance, θJA (see Note1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67oC/W D (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73oC/W DW (SOIC) Package . . . . . . . . . . . . . . . . . . . . . . . . . .
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CD4049UB, CD4050B DC Electrical Specifications (Continued) LIMITS AT INDICATED TEMPERATURE (oC) 25 TEST CONDITIONS PARAMETER Input High Voltage, VIH Min CD4049UB Input High Voltage, VIH Min CD4050B Input Current, IIN Max VO (V) VIN (V) VCC (V) -55 -40 85 125 MIN TYP MAX UNITS 0.5 - 5 4 4 4 4 4 - - V 1 - 10 8 8 8 8 8 - - V 1.5 - 15 12.5 12.5 12.5 12.5 12.5 - - V 4.5 - 5 3.5 3.5 3.5 3.5 3.5 - - V 9 - 10 7 7 7 7 7 - - V 13.
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CD4049UB, CD4050B AC Electrical Specifications TA = 25oC, Input tr , tf = 20ns, CL = 50pF, RL = 200kΩ (Continued) TEST CONDITIONS LIMITS (ALL PACKAGES) VIN VCC TYP MAX UNITS Input Capacitance, CIN CD4049UB - - 15 22.5 pF Input Capacitance, CIN CD4050B - - 5 7.
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CD4049UB, CD4050B Typical Performance Curves (Continued) VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 -1 VDS, DRAIN TO SOURCE VOLTAGE (V) -8 -7 -6 -5 -4 -3 -2 0 -20 -25 -10V -30 -15V -10 VGS = -5V -15 -10V -20 -15V -25 -30 -35 OUTPUT HIGH (SOURCE) -15 GATE TO SOURCE VOLTAGE CURRENT CHARACTERISTICS -10 GATE TO SOURCE VOLTAGE VGS = -5V -35 FIGURE 6. TYPICAL OUTPUT HIGH (SOURCE) CURRENT CHARACTERISTICS FIGURE 7.
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CD4049UB, CD4050B POWER DISSIPATION PER INVERTER (µW) Typical Performance Curves (Continued) 106 TA = 25oC 105 15V; 1MHz 15V; 100kHz 10V; 100kHz 15V; 10kHz 10V; 10kHz 15V; 1kHz 104 103 102 10 SUPPLY VOLTAGE VCC = 5V FREQUENCY (f) = 10kHz 1 10 102 103 104 105 106 107 tr, tf , INPUT RISE AND FALL TIME (ns) 108 FIGURE 12.
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CD4049UB, CD4050B (Continued) VDD 0.1µF 500µF CL 10kHz, 100kHz, 1MHz I 1 2 3 4 5 6 7 8 CD4049UB Test Circuits 16 15 14 13 12 11 10 9 CL INCLUDES FIXTURE CAPACITANCE FIGURE 17.
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CD4049UB, CD4050B 9
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD4049UBDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4049UBDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 CD4049UBNSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4049UBDR CD4049UBDWR SOIC D 16 2500 333.2 345.9 28.6 SOIC DW 16 2000 346.0 346.0 33.0 CD4049UBNSR SO NS 16 2000 346.0 346.0 33.0 CD4049UBPWR TSSOP PW 16 2000 346.0 346.0 29.0 CD4050BDR SOIC D 16 2500 333.2 345.9 28.6 CD4050BDWR SOIC DW 16 2000 346.0 346.0 33.
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MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 24-Jan-2013 Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Only one of markings shown within the brackets will appear on the physical device.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD4049UBDR Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD4049UBDWR SOIC DW 16 2000 330.0 16.4 10.75 10.7 2.7 12.0 16.0 Q1 CD4049UBPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 8-Apr-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4049UBDR SOIC D 16 2500 333.2 345.9 28.6 CD4049UBDWR SOIC DW 16 2000 367.0 367.0 38.0 CD4049UBPWR TSSOP PW 16 2000 367.0 367.0 35.0 CD4050BDR SOIC D 16 2500 333.2 345.9 28.6 CD4050BDWR SOIC DW 16 2000 367.0 367.0 38.0 CD4050BPWR TSSOP PW 16 2000 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.