Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate OR gate 4000B PDIP 14

MOTOROLA CMOS LOGIC DATA

MC14001B

The B Series logic gates are constructed with P and N channel

enhancement mode devices in a single monolithic structure (Complemen-

tary MOS). Their primary use is where low power dissipation and/or high

noise immunity is desired.

• Supply Voltage Range = 3.0 Vdc to 18 Vdc

• All Outputs Buffered

• Capable of Driving Two Low–power TTL Loads or One Low–power

Schottky TTL Load Over the Rated Temperature Range.

• Double Diode Protection on All Inputs Except: Triple Diode Protection

on MC14011B and MC14081B

• Pin–for–Pin Replacements for Corresponding CD4000 Series B Suffix

Devices (Exceptions: MC14068B and MC14078B)

L SUFFIX

CERAMIC

CASE 632

ORDERING INFORMATION

MC14XXXBCP Plastic

MC14XXXBCL Ceramic

MC14XXXBD SOIC

= – 55° to 125°C for all packages.

P SUFFIX

PLASTIC

CASE 646

D SUFFIX

SOIC

CASE 751A

MAXIMUM RATINGS* (Voltages Referenced to V

)

Symbol Parameter Value Unit

DC Supply Voltage – 0.5 to + 18.0 V

, V

out

Input or Output Voltage (DC or Transient) – 0.5 to V

+ 0.5 V

, l

out

Input or Output Current (DC or Transient),

per Pin

± 10 mA

Power Dissipation, per Package† 500 mW

stg

Storage Temperature – 65 to + 150

Lead Temperature (8–Second Soldering) 260

* Maximum Ratings are those values beyond which damage to the device may occur.

†Temperature Derating:

Plastic “P and D/DW” Packages: – 7.0 mW/ C From 65 C To 125 C

Ceramic “L” Packages: – 12 mW/ C From 100 C To 125 C

This device contains protection circuitry to guard against damage

due to high static voltages or electric fields. However, precautions must

be taken to avoid applications of any voltage higher than maximum rated

voltages to this high-impedance circuit. For proper operation, V

and

out

should be constrained to the range V

≤ (V

or V

out

) ≤ V

Unused inputs must always be tied to an appropriate logic voltage

level (e.g., either V

or V

). Unused outputs must be left open.

SEMICONDUCTOR TECHNICAL DATA

 Motorola, Inc. 1995

REV 3

1/94

Summary of content (11 pages)

PAGE 1
SEMICONDUCTOR TECHNICAL DATA % !%$ $ % & " # $ # The B Series logic gates are constructed with P and N channel enhancement mode devices in a single monolithic structure (Complementary MOS). Their primary use is where low power dissipation and/or high noise immunity is desired. • Supply Voltage Range = 3.
PAGE 2
LOGIC DIAGRAMS NAND OR AND MC14001B Quad 2–Input NOR Gate MC14011B Quad 2–Input NAND Gate MC14071B Quad 2–Input OR Gate MC14081B Quad 2–Input AND Gate 2 INPUT NOR 1 2 3 1 2 3 1 2 3 1 2 3 5 6 4 5 6 4 5 6 4 5 6 4 8 9 10 8 9 10 8 9 10 8 9 10 12 13 11 12 13 11 12 13 11 12 13 11 3 INPUT MC14025B Triple 3–Input NOR Gate 1 2 8 3 4 5 11 12 13 9 6 10 4 INPUT MC14002B Dual 4–Input NOR Gate 2 3 4 5 9 10 11 12 1 13 NC = 6, 8 MC14023B Triple 3–Input NAND Gate 1 2 8 3 4 5
PAGE 3
PIN ASSIGNMENTS MC14001B Quad 2–Input NOR Gate MC14002B Dual 4–Input NOR Gate IN 1A 1 14 VDD OUTA 1 14 VDD MC14011B Quad 2–Input NAND Gate MC14012B Dual 4–Input NAND Gate IN 1A 1 14 VDD OUTA 1 14 VDD IN 2A 2 13 IN 2D IN 1A 2 13 OUTB IN 2A 2 13 IN 2D IN 1A 2 13 OUTB OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTA 3 12 IN 1D IN 2A 3 12 IN 4B OUTB 4 11 OUTD IN 3A 4 11 IN 3B OUTB 4 11 OUTD IN 3A 4 11 IN 3B IN 1B 5 10 OUTC IN 4A 5 10 IN 2B IN 1B
PAGE 4
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎ
PAGE 5
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎÎ ÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
PAGE 6
CIRCUIT SCHEMATIC NOR, OR GATES MC14001B, MC14071B One of Four Gates Shown VDD 14 VDD 1, 6, 8, 13 * 2, 5, 9, 12 3, 4, 10, 11 MC14025B, MC14075B One of Three Gates Shown VSS 7 VDD VSS 1, 3, 11 * Inverter omitted in MC14001B 2, 4, 12 14 VDD * MC14002B, MC14072B One of Two Gates Shown VSS 9, 6, 10 VDD VDD 3, 9 8, 5, 13 2, 10 14 7 VDD VSS * * Inverter omitted in MC14025B 1, 13 VSS 5, 11 4, 12 VSS SAME AS ABOVE 7 VSS * Inverter omitted in MC14002B VDD 2 MC14078B Eight Input Gate 3
PAGE 7
CIRCUIT SCHEMATIC NAND, AND GATES MC14011B, MC14081B One of Four Gates Shown 14 VDD * MC14023B, MC14073B One of Three Gates Shown 3, 4, 10, 11 VDD 2, 5, 9, 12 1, 6, 8, 13 7 VSS * Inverter omitted in MC14011B 2, 4, 12 1, 3, 11 14 VSS VDD * VDD 9, 6, 10 MC14012B, MC14082B One of Two Gates Shown 8, 5, 13 7 VSS VDD VSS * Inverter omitted in MC14023B 14 VDD MC14068B Eight Input Gate VDD 2, 10 * 3, 9 VSS VDD 4, 12 5, 11 1, 13 SAME AS ABOVE 2 * Inverter omitted in MC14012B 7 VSS 3 VSS
PAGE 8
TYPICAL B–SERIES GATE CHARACTERISTICS N–CHANNEL DRAIN CURRENT (SINK) P–CHANNEL DRAIN CURRENT (SOURCE) – 10 5.0 ID , DRAIN CURRENT (mA) ID , DRAIN CURRENT (mA) – 9.0 4.0 TA = – 55°C 3.0 – 40°C + 85°C + 25°C 2.0 + 125°C 1.0 – 8.0 TA = – 55°C – 7.0 – 40°C – 6.0 – 5.0 + 25°C + 85°C – 4.0 – 3.0 + 125°C – 2.0 – 1.0 0 0 1.0 2.0 3.0 4.0 VDS, DRAIN–TO–SOURCE VOLTAGE (Vdc) 0 5.0 0 Figure 2. VGS = 5.
PAGE 9
TYPICAL B–SERIES GATE CHARACTERISTICS (cont’d) V out , OUTPUT VOLTAGE (Vdc) V out , OUTPUT VOLTAGE (Vdc) VOLTAGE TRANSFER CHARACTERISTICS SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 5.0 4.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 3.0 2.0 1.0 0 0 1.0 2.0 SINGLE INPUT NAND, AND MULTIPLE INPUT NOR, OR 10 8.0 SINGLE INPUT NOR, OR MULTIPLE INPUT NAND, AND 6.0 4.0 2.0 0 3.0 4.0 5.0 Vin, INPUT VOLTAGE (Vdc) 0 2.0 Figure 8. VDD = 5.0 Vdc V out , OUTPUT VOLTAGE (Vdc) 6.0 8.
PAGE 10
OUTLINE DIMENSIONS L SUFFIX CERAMIC DIP PACKAGE CASE 632–08 ISSUE Y –A– 14 9 1 7 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMENSION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. –B– C –T– L K SEATING PLANE F G D N M J 14 PL 0.25 (0.010) M T A S 14 PL 0.25 (0.
PAGE 11
OUTLINE DIMENSIONS D SUFFIX PLASTIC SOIC PACKAGE CASE 751A–03 ISSUE F NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. –A– 14 8 –B– 1 P 7 PL 0.25 (0.010) 7 G M F –T– 0.25 (0.