Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate XNOR gate 4000B SOIC 14

Data sheet acquired from Harris Semiconductor

SCHS055E

Features

• High-Voltage Types (20V Rating)

• CD4070B - Quad Exclusive-OR Gate

• CD4077B - Quad Exclusive-NOR Gate

• Medium Speed Operation

-t

PHL

, t

PLH

= 65ns (Typ) at V

= 10V, C

= 50pF

• 100% Tested for Quiescent Current at 20V

• Standardized Symmetrical Output Characteristics

• 5V, 10V and 15V Parametric Ratings

• Maximum Input Current of 1µA at 18V Over Full

Package Temperature Range

- 100nA at 18V and 25

• Noise Margin (Over Full Package Temperature Range)

- 1V at V

= 5V, 2V at V

= 10V, 2.5V at V

= 15V

• Meets All Requirements of JEDEC Standard No. 13B,

“Standard Speciﬁcations for Description of ‘B’ Series

CMOS Devices

Applications

• Logical Comparators

• Adders/Subtractors

• Parity Generators and Checkers

Description

The Harris CD4070B contains four independent Exclusive-

OR gates. The Harris CD4077B contains four independent

Exclusive-NOR gates.

The CD4070B and CD4077B provide the system designer

with a means for direct implementation of the Exclusive-OR

and Exclusive-NOR functions, respectively.

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD4070BE -55 to 125 14 Ld PDIP

CD4070BF3A -55 to 125 14 Ld CERDIP

CD4070BM -55 to 125 14 Ld SOIC

CD4070BMT -55 to 125 14 Ld SOIC

CD4070BM96 -55 to 125 14 Ld SOIC

CD4070BNSR -55 to 125 14 Ld SOP

CD4070BPW -55 to 125 14 Ld TSSOP

CD4070BPWR -55 to 125 14 Ld TSSOP

CD4077BE -55 to 125 14 Ld PDIP

CD4077BF3A -55 to 125 14 Ld CERDIP

CD4077BM -55 to 125 14 Ld SOIC

CD4077BMT -55 to 125 14 Ld SOIC

CD4077BM96 -55 to 125 14 Ld SOIC

CD4077BNSR -55 to 125 14 Ld SOP

CD4077BPW -55 to 125 14 Ld TSSOP

CD4077BPWR -55 to 125 14 Ld TSSOP

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD4070B,

CD4077B

CMOS Quad Exclusive-OR

and Exclusive-NOR Gate

[ /Title

(CD40

70B,

CD407

7B)

/Sub-

ject

(CMO

SQuad

Exclu-

sive-

and

Exclu-

sive-

NOR

Gate)

/Autho

r ()

/Key-

words

(Har-

ris

Semi-

con-

ductor,

CD400

metal

gate,

CMOS

, pdip,

cerdip,

mil,

January 1998 - Revised September 2003

Summary of content (30 pages)

PAGE 1
[ /Title (CD40 70B, CD407 7B) /Subject (CMO S Quad ExclusiveOR and ExclusiveNOR Gate) /Autho r () /Keywords (Harris Semiconductor, CD400 0, metal gate, CMOS , pdip, cerdip, mil, CD4070B, CD4077B Data sheet acquired from Harris Semiconductor SCHS055E CMOS Quad Exclusive-OR and Exclusive-NOR Gate January 1998 - Revised September 2003 Features Ordering Information • High-Voltage Types (20V Rating) PART NUMBER • CD4070B - Quad Exclusive-OR Gate TEMP.
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CD4070B, CD4077B Pinouts CD4070B (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW CD4077B (PDIP, CERDIP, SOIC, SOP, TSSOP) TOP VIEW A 1 14 VDD A 1 14 VDD B 2 13 H B 2 13 H J=A⊕B 3 12 G J=A⊕B 3 12 G K=C⊕D 4 11 M = G ⊕ H K=C⊕D 4 11 M = G ⊕ H C 5 10 L = E ⊕ F C 5 10 L = E ⊕ F D 6 9 F D 6 9 F VSS 7 8 E VSS 7 8 E Functional Diagrams CD4070B A J=A⊕B K=C⊕D M=G⊕ H L=E⊕F VSS = 7 VDD = 14 B C D E F G H 1 CD4077B 3 2 5 9 12 13 B J =A 4 6 8 A J 10 11 K=C K L ⊕B ⊕D ⊕H =E⊕F C D
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CD4070B, CD4077B VDD VDD VDD p VDD B† p 2(5,9,12) n p 1(6,8,13) n p n J p n 3(4,10,11) n VDD n p p J VDD p VSS † n VSS VDD A† 2(5,9,12) n VSS p B† p A† p 1(6,8,13) n n VSS VSS † INPUTS PROTECTED BY CMOS PROTECTION NETWORK 3(4,10,11) n VSS VDD INPUTS PROTECTED BY CMOS PROTECTION NETWORK VSS VSS FIGURE 1. SCHEMATIC DIAGRAM FOR CD4070B (1 OF 4 IDENTICAL GATES) FIGURE 2.
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CD4070B, CD4077B Absolute Maximum Ratings Thermal Information DC Supply Voltage Range (VDD) . . . . . . . . . . . . . . . . . -0.5V to 20V Input Voltage Range, All Inputs . . . . . . . . . . . . . . -0.5V to VDD 0.5V DC Input Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .± 10mA Package Thermal Impedance, θJA (see Note 1): E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80oC/W M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . .
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CD4070B, CD4077B AC Electrical Specifications TA = 25oC, Input tr, tf = 20ns, CL = 50pF, RL = 200kΩ TEST CONDITIONS PARAMETER Propagation Delay Time Transition Time SYMBOL VDD (V) TYP MAX UNITS tPHL, tPLH 5 140 280 ns 10 65 130 ns 15 50 100 ns 5 100 200 ns 10 50 100 ns 15 40 80 ns Any Input 5 7.
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(Continued) tPHL, tPLH, PROPAGATION DELAY TIME (ns) tTHL, tTLH, TRANSITION TIME (ns) Typical Performance Curves TA = 25oC 200 SUPPLY VOLTAGE (VDD) = 5V 150 100 10V 50 15V 0 0 20 40 60 80 100 TA = 25oC 300 200 SUPPLY VOLTAGE (VDD) = 5V 100 10V 15V 0 0 110 20 105 TA = 25oC LOAD CAPACITANCE CL = 50pF 300 200 100 0 5 10 15 60 80 100 FIGURE 8.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD4070BM96 Package Package Pins Type Drawing SOIC SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD4070BPWR TSSOP PW 14 2000 330.0 12.4 7.0 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 11-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4070BM96 SOIC D 14 2500 346.0 346.0 33.0 CD4070BNSR SO NS 14 2000 346.0 346.0 33.0 CD4070BPWR TSSOP PW 14 2000 346.0 346.0 29.0 CD4077BM96 SOIC D 14 2500 346.0 346.0 33.0 CD4077BNSR SO NS 14 2000 346.0 346.0 33.0 CD4077BPWR TSSOP PW 14 2000 346.0 346.0 29.
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MECHANICAL DATA MTSS001C – JANUARY 1995 – REVISED FEBRUARY 1999 PW (R-PDSO-G**) PLASTIC SMALL-OUTLINE PACKAGE 14 PINS SHOWN 0,30 0,19 0,65 14 0,10 M 8 0,15 NOM 4,50 4,30 6,60 6,20 Gage Plane 0,25 1 7 0°– 8° A 0,75 0,50 Seating Plane 0,15 0,05 1,20 MAX PINS ** 0,10 8 14 16 20 24 28 A MAX 3,10 5,10 5,10 6,60 7,90 9,80 A MIN 2,90 4,90 4,90 6,40 7,70 9,60 DIM 4040064/F 01/97 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD4070BM96 SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 6.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 CD4070BMT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD4070BNSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD4070BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4070BMT SOIC D 14 250 367.0 367.0 38.0 CD4070BNSR SO NS 14 2000 367.0 367.0 38.0 CD4070BPWR TSSOP PW 14 2000 367.0 367.0 35.0 CD4077BM96 SOIC D 14 2500 367.0 367.0 38.0 CD4077BMT SOIC D 14 250 367.0 367.0 38.0 CD4077BNSR SO NS 14 2000 367.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.