Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter NOR gate 74AC SOIC 14

CD54AC02, CD74AC02

QUADRUPLE 2-INPUT POSITIVE-NOR GATES

SCHS304C – JANUARY 2001 – REVISED JUNE 2002

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply Voltage

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description

The ’AC02 devices contain four independent 2-input NOR gates that perform the Boolean function Y = A B

or Y = A + B in positive logic.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E Tube CD74AC02E CD74AC02E

55°Cto125°C

SOIC M

Tube CD74AC02M

AC02M

–

55°C

125°C

SOIC

–

Tape and reel CD74AC02M96

AC02M

CDIP – F Tube CD54AC02F3A CD54AC02F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB

design guidelines are available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

H X L

X HL

L L H

logic diagram (positive logic)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

GND

CD54AC02 ...F PACKAGE

CD74AC02 ...E OR M PACKAGE

(TOP VIEW)

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
CD54AC02, CD74AC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCHS304C – JANUARY 2001 – REVISED JUNE 2002 D D D D D D CD54AC02 . . . F PACKAGE CD74AC02 . . . E OR M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.
PAGE 2
CD54AC02, CD74AC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCHS304C – JANUARY 2001 – REVISED JUNE 2002 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 3
CD54AC02, CD74AC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCHS304C – JANUARY 2001 – REVISED JUNE 2002 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = –50 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –24 mA IOH = –50 mA† IOH = –75 mA† IOL = 50 µA VOL II ICC VI = VIH or VIL VI = VCC or GND VI = VCC or GND, VCC TA = 25°C –40°C TO 85°C –55°C TO 125°C MIN MIN MIN MAX MAX 1.5 V 1.4 1.4 1.4 3V 2.9 2.9 2.
PAGE 4
CD54AC02, CD74AC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCHS304C – JANUARY 2001 – REVISED JUNE 2002 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) A or B Y –40°C TO 85°C –55°C TO 125°C MIN MAX MIN MAX 3 10.4 2.9 11.5 3 10.4 2.9 11.
PAGE 5
CD54AC02, CD74AC02 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCHS304C – JANUARY 2001 – REVISED JUNE 2002 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω† From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω† TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw VCC † When VCC = 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC02M96 Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC02M96 SOIC D 14 2500 367.0 367.0 38.
PAGE 10
PAGE 11
PAGE 12
PAGE 13
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.