Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 16

CD54AC109, CD74AC109

DUAL J-K

POSITIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS326 – JANUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply Voltage

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description/ordering information

The ’AC109 devices contain two independent J-K positive-edge-triggered flip-flops. A low level at the preset

(PRE

) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements are transferred to

the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and

is not directly related to the rise time of the clock pulse. Following the hold-time interval, data at the J and K

inputs

can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by grounding K

and tying J high. They also can perform as D-type flip-flops if J and K are tied together.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E Tube CD74AC109E CD74AC109E

–55°C to 125°C

SOIC – M Tape and reel CD74AC109M96 AC109M

CDIP – F Tube CD54AC109F3A CD54AC109F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

CD54AC109 ...F PACKAGE

CD74AC109 ...E OR M PACKAGE

(TOP VIEW)

1CLR

1CLK

1PRE

GND

2CLR

2CLK

2PRE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 D D D D D D CD54AC109 . . . F PACKAGE CD74AC109 . . . E OR M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.
PAGE 2
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 FUNCTION TABLE (each flip-flop) INPUTS OUTPUTS PRE CLR CLK J K Q Q L H X X X H L H L X X X L H L L X X X H† H† H H ↑ L L L H H H ↑ H L H H ↑ L H H H ↑ H H H L H H L X X Q0 Q0 Toggle Q0 Q0 † Unpredictable and unstable condition if both PRE and CLR go low simultaneously logic diagram, each flip-flop (positive logic) PRE C J C Q TG TG
PAGE 3
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN IOH = –50 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –24 mA IOH = –50 mA† IOH = –75 mA† IOL = 50 µA VOL II ICC VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C MAX MIN –40°C to 85°C MAX MIN 1.5 V 1.4 1.4 1.4 2.9 3V 2.
PAGE 5
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) –55°C to 125°C MIN fclock Clock frequency tw Pulse duration tsu th trec –40°C to 85°C MAX MIN 71 CLK high or low UNIT MAX 81 MHz 7 6 CLR or PRE 6.3 5.5 Setup time, before CLK↑ J or K 7.7 6.
PAGE 6
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL –55°C to 125°C MIN MAX 100 CLK Q or Q CLR or PRE CLK Q or Q CLR or PRE –40°C to 85°C MIN UNIT MAX 114 MHz 2.6 10.3 2.7 9.4 3.1 12.2 3.2 11.1 2.6 10.3 2.7 9.4 3.1 12.2 3.
PAGE 7
CD54AC109, CD74AC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS326 – JANUARY 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω† From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω† TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw VCC † When VCC = 1.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC109M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC109M96 SOIC D 16 2500 333.2 345.9 28.
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