Datasheet

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CD74AC175

QUADRUPLE D-TYPE FLIP-FLOP

WITH CLEAR

SCHS347 – APRIL 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply Voltage

Buffered Inputs

Contains Four Flip-Flops With Double-Rail

Outputs

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

Applications Include:

– Buffer/Storage Registers

– Shift Registers

– Pattern Generators

description/ordering information

This positive-edge-triggered D-type flip-flop has a direct clear (CLR) input. The CD74AC175 features

complementary outputs from each flip-flop.

Information at the data (D) inputs meeting the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low

level, the D input has no effect at the output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

Cto125

SOIC M

Tube CD74AC175M

AC175M

–

55°C

125°C

SOIC

–

Tape and reel CD74AC175M96

AC175M

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

CLR CLK D Q Q

L X X L H

H ↑ HHL

H ↑ LLH

H L X Q

M PACKAGE

(TOP VIEW)

CLR

GND

CLK

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (13 pages)

PAGE 1
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 D D D D D D D D D M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.
PAGE 2
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 logic diagram (positive logic) CLR CLK 1D 1 9 4 2 1D 1Q C1 3 R 1Q To Three Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . .
PAGE 3
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN IOH = –50 µA VOH VI = VIH or VIL IOH = –4 mA IOH = –24 mA IOH = –50 mA† IOH = –75 mA† IOL = 50 µA VOL II ICC VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C MAX MIN –40°C to 85°C MAX MIN 1.5 V 1.4 1.4 1.4 2.9 3V 2.9 2.9 4.5 V 4.4 4.4 4.4 3V 2.
PAGE 4
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 timing requirements over recommended operating free-air temperature range, VCC = 3.3 V ± 0.3 V (unless otherwise noted) –55°C to 125°C MIN fclock Clock frequency tw Pulse duration tsu th Setup time before CLK↑ trec Recovery time, before CLK↑ –40°C to 85°C MAX MIN 71 CLR low UNIT MAX 81 MHz 5.6 4.9 CLK high or low 7 6.
PAGE 5
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) –55°C to 125°C MIN MAX 100 CLK Any Q CLR Any Q –40°C to 85°C MIN UNIT MAX 114 MHz 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.1 3.1 12.2 3.2 11.
PAGE 6
CD74AC175 QUADRUPLE D-TYPE FLIP-FLOP WITH CLEAR SCHS347 – APRIL 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω† From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω† TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw VCC † When VCC = 1.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC175M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC175M96 SOIC D 16 2500 333.2 345.9 28.
PAGE 11
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PAGE 13
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