Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate and inverter XOR gate 74AC SOIC 14

CD74AC86

QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE

SCHS324 – JANUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

AC Types Feature 1.5-V to 5.5-V Operation

and Balanced Noise Immunity at 30% of the

Supply

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description/ordering information

The CD74AC86 is a quadruple 2-input exclusive-OR gate. This device performs the Boolean function

Y = A ⊕ B or Y = A

B + AB in positive logic.

A common application is as a true/complement element. If one of the inputs is low, the other input is reproduced

in true form at the output. If one of the inputs is high, the signal on the other input is reproduced inverted at the

output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E Tube CD74AC86E CD74AC86E

–55°C to 125°C

SOIC – M

Tube CD74AC86M

AC86M

SOIC

–

Tape and reel CD74AC86M96

AC86M

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each gate)

INPUTS

OUTPUT

A B

L L L

L HH

H LH

H H L

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E OR M PACKAGE

(TOP VIEW)

GND

Summary of content (13 pages)

PAGE 1
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003 D D D D D D E OR M PACKAGE (TOP VIEW) AC Types Feature 1.5-V to 5.
PAGE 2
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003 exclusive-OR logic An exclusive-OR gate has many applications, some of which can be represented better by alternative logic symbols. EXCLUSIVE OR =1 These are five equivalent exclusive-OR symbols valid for an CD74AC86 gate in positive logic; negation may be shown at any two ports. LOGIC-IDENTITY ELEMENT = The output is active (low) if all inputs stand at the same logic level (i.e., A = B).
PAGE 3
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003 recommended operating conditions (see Note 3) –55°C to 125°C TA = 25°C VCC Supply voltage VIH High-level input voltage UNIT MIN MAX MIN MAX MIN MAX 1.5 5.5 1.5 5.5 1.5 5.5 VCC = 1.5 V VCC = 3 V 1.2 1.2 1.2 2.1 2.1 2.1 VCC = 5.5 V VCC = 1.5 V 3.85 VIL Low-level input voltage VI VO Input voltage 0 Output voltage 0 IOH IOL High-level output current ∆t/∆v Input transition rise or fall rate 3.
PAGE 4
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 1.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER tPLH tPHL FROM (INPUT) TO (OUTPUT) A or B Y –55°C to 125°C MIN MAX –40°C TO 85°C MIN UNIT MAX 135 123 135 123 ns switching characteristics over recommended operating free-air temperature range, VCC = 3 V ± 0.
PAGE 5
CD74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATE SCHS324 – JANUARY 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω† From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω† TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw VCC † When VCC = 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74AC86M96 Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 9.0 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74AC86M96 SOIC D 14 2500 367.0 367.0 38.
PAGE 10
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.