Datasheet

CD74ACT10
TRIPLE 3-INPUT POSITIVE-NAND GATES
SCHS316 – NOVEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
D Inputs Are TTL-Voltage Compatible
D Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
D Balanced Propagation Delays
D ±24-mA Output Drive Current
– Fanout to 15 F Devices
D SCR Latchup-Resistant CMOS Process and
Circuit Design
D Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The CD74ACT10 contains three independent 3-input NAND gates. The device performs the Boolean functions
Y = A
• B • C or Y = A + B + C in positive logic.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube CD74ACT10E CD74ACT10E
–55°C to 125°C
SOIC M
Tube CD74ACT10M
ACT10M
SOIC – M
Tape and Reel CD74ACT10M96
ACT10M
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B C
OUTPUT
Y
H H H L
L XX H
X LX H
X X L H
logic diagram, each gate (positive logic)
Y
A
B
C
E OR M PACKAGE
(TOP VIEW)
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
2A
2B
2C
2Y
GND
V
CC
1C
1Y
3C
3B
3A
3Y
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright  2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.