Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 16

CD54ACT112, CD74ACT112

DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS

WITH CLEAR AND PRESET

SCHS323 – JANUARY 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

description/ordering information

The ’ACT112 devices contain two independent J-K negative-edge-triggered flip-flops. A low level at the preset

(PRE

) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE

and CLR are inactive (high), data at the J and K inputs meeting the setup-time requirements is transferred to

the outputs on the negative-going edge of the clock pulse (CLK). Clock triggering occurs at a voltage level and

is not directly related to the fall time of the clock pulse. Following the hold-time interval, data at the J and K inputs

may be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle

flip-flops by tying J and K high.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

SOIC M

Tube CD74ACT112M

ACT112M

–55°C to 125°C

SOIC

–

Tape and reel CD74ACT112M96

ACT112M

CDIP – F Tube CD54ACT112F3A CD54ACT112F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUTS

PRE CLR CLK J K Q Q

L H X X X H L

H LXXXLH

L LXXXH

‡

H H ↓ LLQ

H H ↓ HLHL

H H ↓ LHLH

H H ↓ H H Toggle

H H H X X Q

‡

Output states are unpredictable if PRE

and CLR go high

simultaneously after both being low at the same time.

CD54ACT112 ...F PACKAGE

CD74ACT112 ...M PACKAGE

(TOP VIEW)

1CLK

1PRE

GND

1CLR

2CLR

2CLK

2PRE

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (13 pages)

PAGE 1
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 D D D D D D CD54ACT112 . . . F PACKAGE CD74ACT112 . . .
PAGE 2
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 logic diagram (positive logic) Q Q PRE CLR J K CLK absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . .
PAGE 3
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH VOL II ICC DICC VI = VIH or VIL VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C VCC MAX MIN –40°C to 85°C MAX MIN UNIT MAX IOH = –50 µA IOH = –24 mA 4.5 V 4.4 4.5 V 3.94 IOH = –50 mA† IOH = –75 mA† 5.
PAGE 4
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax tPLH tPHL –55°C to 125°C MIN MAX 100 CLK Q or Q CLR or PRE CLK Q or Q CLR or PRE –40°C to 85°C MIN UNIT MAX 114 MHz 2.6 10.3 2.7 9.4 3.1 12.2 3.2 11.1 2.6 10.3 2.7 9.4 3.1 12.2 3.
PAGE 5
CD54ACT112, CD74ACT112 DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCHS323 – JANUARY 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74ACT112M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74ACT112M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.