Datasheet

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CD54ACT161, CD74ACT161

4-BIT SYNCHRONOUS BINARY COUNTERS

SCHS298B – APRIL 2000 – REVISED MARCH 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Internal Look-Ahead for Fast Counting

Carry Output for n-Bit Cascading

Synchronous Counting

Synchronously Programmable

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection per

MIL-STD-883, Method 3015

description/ordering information

The ’ACT161 devices are 4-bit binary counters. These synchronous, presettable counters feature an internal

carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having

all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed

by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output

counting spikes that normally are associated with synchronous (ripple-clock) counters. A buffered clock (CLK)

input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform.

These devices are fully programmable; that is, they can be preset to any number between 0 and 9 or 15.

Presetting is synchronous; therefore, setting up a low level at the load input disables the counter and causes

the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.

The clear function is asynchronous. A low level at the clear (CLR

) input sets all four of the flip-flop outputs low,

regardless of the levels of the CLK, load (LOAD), or enable inputs.

The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without

additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO).

Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a

high-level pulse while the count is maximum (9 or 15, with Q

high). This high-level overflow ripple-carry pulse

can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the

level of CLK.

The counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD

) that

modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of

the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the

stable setup and hold times.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E Tube CD74ACT161E CD74ACT161E

55°Cto125°C

SOIC M

Tube CD74ACT161M

ACT161M

–

55°C

125°C

SOIC

–

Tape and reel CD74ACT161M96

ACT161M

CDIP – F Tube CD54ACT161F3A CD54ACT161F3A

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

CLR

CLK

ENP

GND

RCO

ENT

LOAD

CD54ACT161 ...F PACKAGE

CD74ACT161 ...E OR M PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (17 pages)

PAGE 1
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 D D D D D D D CD54ACT161 . . . F PACKAGE CD74ACT161 . . .
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CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 FUNCTION TABLE INPUTS OUTPUTS CLR CLK ENP ENT LOAD A,B,C,D Qn RCO L X X X X X L L H ↑ X X l l L L H ↑ X X l h H Note 1 H ↑ h h h X Count Note 1 H X l X h X Note 1 H X X l h X qn qn L FUNCTION Reset (clear) Parallel load Count Inhibit H = high level, L = low level, X = don’t care, h = high level one setup time prior to the CLK low-to-high transition, l
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CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram.
PAGE 4
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 1, 2T/1C3 G4 CK (Clock) D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the logic diagram of the overall device.
PAGE 5
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4.
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CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 7
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC MIN VOH VOL II ICC DICC‡ VI = VIH or VIL VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C MAX MIN –40°C to 85°C MAX MIN UNIT MAX IOH = –50 µA IOH = –24 mA 4.5 V 4.4 4.5 V IOH = –50 mA† IOH = –75 mA† 5.
PAGE 8
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 switching characteristics over recommended operating conditions, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax MIN MAX 80 CLK tpd –55°C to 125°C ENT CLR –40°C to 85°C MIN UNIT MAX 91 MHz RCO 4.2 16.7 4.3 Any Q 4.1 16.5 4.2 15.2 15 RCO 2.7 10.8 2.8 9.8 Any Q 4.1 16.5 4.2 15 RCO 4.1 16.5 4.
PAGE 9
CD54ACT161, CD74ACT161 4-BIT SYNCHRONOUS BINARY COUNTERS SCHS298B – APRIL 2000 – REVISED MARCH 2003 PARAMETER MEASUREMENT INFORMATION 2 × VCC S1 R1 = 500 Ω From Output Under Test Open GND R2 = 500 Ω CL = 50 pF (see Note A) TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V NOTE: When VCC = 1.5 V, R1 and R2 = 1 kΩ. Input 1.5 V 1.5 V LOAD CIRCUIT 0V VOLTAGE WAVEFORMS PULSE DURATION 3V CLR Input 3V Reference Input 1.5 V 0V 1.5 V 0V trec 3V Data Input 1.5 V 10% 1.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74ACT161M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74ACT161M96 SOIC D 16 2500 333.2 345.9 28.
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