Datasheet

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CD54ACT174, CD74ACT174

HEX D-TYPE FLIP-FLOPS

WITH CLEAR

SCHS344 – APRIL 2003

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Inputs Are TTL-Voltage Compatible

Contain Six Flip-Flops With Single-Rail

Outputs

Buffered Inputs

Speed of Bipolar F, AS, and S, With

Significantly Reduced Power Consumption

Balanced Propagation Delays

±24-mA Output Drive Current

– Fanout to 15 F Devices

SCR-Latchup-Resistant CMOS Process and

Circuit Design

Exceeds 2-kV ESD Protection Per

MIL-STD-883, Method 3015

Applications Include:

– Buffer/Storage Registers

– Shift Registers

description/ordering information

The ’ACT174 devices are positive-edge-triggered D-type flip-flops with a direct clear (CLR) input and are

designed for 4.5-V to 5.5-V V

operation.

Information at the data (D) inputs that meets the setup time requirements is transferred to the outputs on the

positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not

directly related to the transition time of the positive-going edge of CLK. When CLK is at either the high or low

level, the D input has no effect at the output.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP – E Tube CD74ACT174E CD74ACT174E

Cto125

SOIC M

Tube CD74ACT174M

ACT174M

–

55°C

125°C

SOIC

–

Tape and reel CD74ACT174M96

ACT174M

CDIP – F Tube CD54ACT174F3A CD54ACT174F3A

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines

are available at www.ti.com/sc/package.

FUNCTION TABLE

(each flip-flop)

INPUTS

OUTPUT

CLR CLK D

L X X L

H ↑ HH

H ↑ LL

H L X Q

CD54ACT174 ...F PACKAGE

CD74ACT174 ...E OR M PACKAGE

(TOP VIEW)

CLR

GND

CLK

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

On products compliant to MIL-PRF-38535, all parameters are tested

unless otherwise noted. On all other products, production

processing does not necessarily include testing of all parameters.

Summary of content (14 pages)

PAGE 1
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 D D D D D D D D D CD54ACT174 . . . F PACKAGE CD74ACT174 . . .
PAGE 2
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 logic diagram (positive logic) CLR CLK 1D 1 9 3 1D 2 C1 1Q R To Five Other Channels absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V Input clamp current, IIK (VI < 0 V or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . .
PAGE 3
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN VOH VOL II ICC DICC‡ VI = VIH or VIL VI = VIH or VIL VI = VCC or GND VI = VCC or GND, –55°C to 125°C TA = 25°C VCC MAX MIN –40°C to 85°C MAX MIN UNIT MAX IOH = –50 µA IOH = –24 mA 4.5 V 4.4 4.5 V 3.94 IOH = –50 mA† IOH = –75 mA† 5.
PAGE 4
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 switching characteristics over recommended operating free-air temperature range, VCC = 5 V ± 0.5 V, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL FROM (INPUT) TO (OUTPUT) –55°C to 125°C MIN –40°C to 85°C MAX 80 CLK Any Q CLR Any Q MIN UNIT MAX 91 MHz 3.5 14 3.6 12.6 3.5 14 3.6 12.6 3.9 15.5 4 14.1 3.9 15.5 4 14.
PAGE 5
CD54ACT174, CD74ACT174 HEX D-TYPE FLIP-FLOPS WITH CLEAR SCHS344 – APRIL 2003 PARAMETER MEASUREMENT INFORMATION S1 R1 = 500 Ω From Output Under Test 2 × VCC Open GND CL = 50 pF (see Note A) R2 = 500 Ω TEST S1 tPLH/tPHL tPLZ/tPZL tPHZ/tPZH Open 2 × VCC GND tw 3V 1.5 V Input LOAD CIRCUIT 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATION CLR Input 3V Reference Input 3V 1.5 V 1.5 V 0V 0V trec Data Input 3V 1.5 V CLK th tsu 1.5 V 10% 90% 90% tr 0V VOLTAGE WAVEFORMS RECOVERY TIME 3V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 8
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74ACT174M96 Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74ACT174M96 SOIC D 16 2500 333.2 345.9 28.
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