Datasheet

CD54ACT20, CD74ACT20
DUAL 4-INPUT POSITIVE-NAND GATES
SCHS320 – NOVEMBER 2002
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Inputs Are TTL-Voltage Compatible
Speed of Bipolar F, AS, and S, With
Significantly Reduced Power Consumption
Balanced Propagation Delays
±24-mA Output Drive Current
– Fanout to 15 F Devices
SCR-Latchup-Resistant CMOS Process and
Circuit Design
Exceeds 2-kV ESD Protection Per
MIL-STD-883, Method 3015
description/ordering information
The ’ACT20 devices contain two independent 4-input NAND gates. They perform the Boolean function
Y = A
• B • C • D or Y = A + B + C + D in positive logic.
ORDERING INFORMATION
T
A
PACKAGE
†
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
PDIP – E Tube CD74ACT20E CD74ACT20E
55°Cto125°C
SOIC M
Tube CD74ACT20M
ACT20M
–
55°C
to
125°C
SOIC
–
M
Tape and reel CD74ACT20M96
ACT20M
CDIP – F Tube CD54ACT20F3A CD54ACT20F3A
†
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
FUNCTION TABLE
(each gate)
INPUTS
OUTPUT
A B C D
Y
H H H H L
L XXX H
X LXX H
X XLX H
X X X L H
logic diagram (positive logic)
1A
1Y
1B
1C
1D
2A
2Y
2B
2C
2D
1
2
4
5
9
10
12
13
68
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1A
1B
NC
1C
1D
1Y
GND
V
CC
2D
2C
NC
2B
2A
2Y
CD54ACT20 ...F PACKAGE
CD74ACT20 ...E OR M PACKAGE
(TOP VIEW)
Copyright  2002, Texas Instruments Incorporated
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.