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CD74FCT374

BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP

WITH 3-STATE OUTPUTS

SCBS739 – JULY 2000

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

BiCMOS Technology With Low Quiescent

Power

3-State Outputs Drive Bus Lines Directly

Buffered Inputs

Noninverted Outputs

Input/Output Isolation From V

Controlled Output Edge Rates

48-mA Output Sink Current

Output Voltage Swing Limited to 3.7 V

SCR Latch-Up-Resistant BiCMOS Process

and Circuit Design

Package Options Include Plastic

Small-Outline (M) and Shrink Small-Outline

(SM) Packages and Standard Plastic (E) DIP

description

The CD74FCT374 is an octal, edge-triggered, D-type flip-flop that uses a small-geometry BiCMOS technology

and features 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance

loads. This device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers,

and working registers.

The output stage is a combination of bipolar and CMOS transistors that limits the output high level to two diode

drops below V

. This resultant lowering of output swing (0 V to 3.7 V) reduces power-bus ringing [a source

of electromagnetic interference (EMI)] and minimizes V

bounce and ground bounce and their effects during

simultaneous output switching. The output configuration also enhances switching speed and is capable of

sinking 48 mA.

The eight flip-flops enter data into their registers on the low-to-high transition of the clock (CLK). The

output-enable (OE) input controls the 3-state outputs and is independent of the register operation. When OE

is high, the outputs are in the high-impedance state.

A buffered OE input can be used to place the eight outputs in either a normal logic state (high or low) or the

high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.

The high-impedance state and the increased drive provide the capability to drive bus lines without interface or

pullup components.

does not affect internal operations of the flip-flop. Old data can be retained or new data can be entered while

the outputs are in the high-impedance state.

To ensure the high-impedance state during power up or power down, OE should be tied to V

through a pullup

resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

The CD74FCT374 is characterized for operation from 0°C to 70°C.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

E, M, OR SM PACKAGE

(TOP VIEW)

GND

CLK

Summary of content (10 pages)

PAGE 1
CD74FCT374 BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS739 – JULY 2000 D D D D D D D D D D E, M, OR SM PACKAGE (TOP VIEW) BiCMOS Technology With Low Quiescent Power 3-State Outputs Drive Bus Lines Directly Buffered Inputs Noninverted Outputs Input/Output Isolation From VCC Controlled Output Edge Rates 48-mA Output Sink Current Output Voltage Swing Limited to 3.
PAGE 2
CD74FCT374 BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS739 – JULY 2000 FUNCTION TABLE (each flip-flop) INPUTS OE CLK D OUTPUT Q L ↑ H H L ↑ L L L H or L X Q0 H X X Z logic symbol† 1 OE CLK 1D 2D 3D 4D 5D 6D 7D 8D 11 3 EN C1 2 1D 4 5 7 6 8 9 13 12 14 15 17 16 18 19 1Q 2Q 3Q 4Q 5Q 6Q 7Q 8Q † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
PAGE 3
CD74FCT374 BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS739 – JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† DC supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 6 V DC input clamp current, IIK (VI < –0.5 V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD74FCT374 BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS739 – JULY 2000 timing requirements over recommended operating conditions, (unless otherwise noted) (see Figure 1) MIN MAX UNIT 70 MHz fclock tw Clock frequency Pulse duration CLK high or low 7 ns tsu Setup time Data before CLK↑ 2 ns th Hold time Data after CLK↑ 2 ns switching characteristics over recommended operating conditions, VCC = 5 V ± 0.
PAGE 5
CD74FCT374 BiCMOS OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS SCBS739 – JULY 2000 PARAMETER MEASUREMENT INFORMATION 7V From Output Under Test CL = 50 pF (see Note A) 500 Ω From Output Under Test Test Point Open TEST GND CL = 50 pF (see Note A) 500 Ω S1 S1 Open 7V Open 7V tPLH/tPHL tPLZ/tPZL tPHZ/tPZH 500 Ω Open Drain LOAD CIRCUIT FOR 3-STATE AND OPEN-DRAIN OUTPUTS LOAD CIRCUIT FOR TOTEM-POLE OUTPUTS 90% 1.5 V 10% 3V 1.
PAGE 6
PACKAGE OPTION ADDENDUM www.ti.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.