Datasheet

M54HC107
M74HC107
October 1992
DUAL J-K FLIP FLOP WITH CLEAR
B1R
(Plastic Package)
ORDER CODES :
M54HC107F1R M74HC107M1R
M74HC107B1R M74HC107C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
INPUT AND OUTPUT EQUIVALENT CIRCUIT
.HIGH SPEED
f
MAX
= 75 MHz (TYP.) AT V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=2µA (MAX.) AT T
A
=25°C
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.SYMMETRICAL OUTPUT IMPEDANCE
IOH =I
OL
= 4 mA (MIN.)
.BALANCEDPROPAGATION DELAYS
t
PLH
=t
PHL
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE WITH
54/74LS107
The M54/74HC107 is a high speed CMOSDUAL J-
K FLIPFLOP fabricated in silicon gate C
2
MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. These flip-flop are edge sensitive to the
clock input and change state on the negative going
transition of the clock pulse. Each one has inde-
pendent J, K, CLOCK, and CLEAR input and Q and
Q outputs. CLEAR is independent of the clock and
accomplished by a logic low on the input. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
DESCRIPTION
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