Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Preset/reset Differential SOIC 16

Data sheet acquired from Harris Semiconductor

SCHS140E

Features

• Asynchronous Set and Reset

• Schmitt Trigger Clock Inputs

• Typical f

MAX

= 54MHz at V

= 5V, C

= 15pF,

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC109, CD54HCT109

(CERDIP)

CD74HC109, CD74HCT109

(PDIP, SOIC)

TOP VIEW

Description

The ’HC109 and ’HCT109 are dual J-K ﬂip-ﬂops with set and

reset. The ﬂip-ﬂop changes state with the positive transition

of Clock (1CP and 2CP).

The ﬂip-ﬂop is set and reset by active-low

S and R,

respectively. A low on both the set and reset inputs

simultaneously will force both Q and

Q outputs high.

However, both set and reset going high simultaneously

results in an unpredictable output condition.

1CP

GND

2CP

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC109F3A -55 to 125 16 Ld CERDIP

CD54HCT109F3A -55 to 125 16 Ld CERDIP

CD74HC109E -55 to 125 16 Ld PDIP

CD74HC109M -55 to 125 16 Ld SOIC

CD74HC109MT -55 to 125 16 Ld SOIC

CD74HC109M96 -55 to 125 16 Ld SOIC

CD74HCT109E -55 to 125 16 Ld PDIP

CD74HCT109M -55 to 125 16 Ld SOIC

CD74HCT109MT -55 to 125 16 Ld SOIC

CD74HCT109M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

March 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC109, CD74HC109,

CD54HCT109, CD74HCT109

Dual J-K Flip-Flop with Set and Reset

Positive-Edge Trigger

[

/Title

(

CD74H

109,

D74H

T109)

Subject

(

Dual J-

Flip-

lop

ith Set

eset

Summary of content (16 pages)

PAGE 1
[ /Title (CD74H C109, CD74H CT109) /Subject (Dual JK FlipFlop with Set and Reset CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Data sheet acquired from Harris Semiconductor SCHS140E Dual J-K Flip-Flop with Set and Reset Positive-Edge Trigger March 1998 - Revised October 2003 Features Description • Asynchronous Set and Reset The ’HC109 and ’HCT109 are dual J-K flip-flops with set and reset. The flip-flop changes state with the positive transition of Clock (1CP and 2CP).
PAGE 2
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Functional Diagram 1S 1J 1K 1CP 1R 2S 2J 2K 2CP 2R 5 2 6 1Q 3 F/F 1 7 1Q 4 1 11 14 10 2Q 13 F/F 2 9 2Q 12 GND = 8 VCC = 16 15 TRUTH TABLE INPUTS OUTPUTS S R CP J K Q Q L H X X X H L H L X X X L H L L X X X H (Note 1) H (Note 1) H H ↑ L L L H H ↑ H L Toggle H H ↑ L H No Change H H ↑ H H H H L X X H H L No Change H= High Level (Steady State) L= Low Level (Steady State) X= Don’t Care ↑= Low
PAGE 3
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±25mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads SYMBOL VI (V) VOL VIH or VIL Low Level Output Voltage TTL Loads 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 0.1 - 0.1 - 0.1 V 4.5 - - 0.1 - 0.1 - 0.1 V 6 - - 0.1 - 0.1 - 0.1 V - - - - - - - - - V 4 4.5 - - 0.26 - 0.33 - 0.4 V 5.2 6 - - 0.26 - 0.
PAGE 5
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Prerequisite For Switching Specifications PARAMETER 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tSU - 2 80 - - 100 - 120 - ns 4.5 16 - - 20 - 24 - ns 6 14 - - 17 - 20 - ns 2 5 - - 5 - 5 - ns 4.5 5 - - 5 - 5 - ns 6 5 - - 5 - 5 - ns 2 80 - - 100 - 120 - ns 4.
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CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Switching Specifications Input tr, tf = 6ns PARAMETER Propagation Delay, R→Q Propagation Delay, R→Q Transition Time Input Capacitance (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 2 - - 185 - 230 - 280 ns CL = 50pF 4.5 - - 37 - 46 - 56 ns CL = 15pF 5 - 15 - - - - - ns CL = 50pF 6 - - 31 - 39 - 48 ns CL = 50pF 2 - - 170 - 215 - 255 ns CL = 50pF 4.
PAGE 7
CD54HC109, CD74HC109, CD54HCT109, CD74HCT109 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 9. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tPLH FIGURE 10. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL 10% tTLH 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 25-Sep-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC109M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT109M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC109M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT109M96 SOIC D 16 2500 333.2 345.9 28.
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