Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate AND gate 74HC PDIP 14

Data sheet acquired from Harris Semiconductor

SCHS273E

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V

= 5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOS

technology to achieve operating speeds similar to LSTTL

gates with the low power consumption of standard CMOS

integrated circuits. All devices have the ability to drive 10

LSTTL loads. The HCT logic family is functionally pin

compatible with the standard LS logic family.

Pinout

CD54HC11, CD54HCT11

(CERDIP)

CD74HC11, CD74HCT11

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC11F3A -55 to 125 14 Ld CERDIP

CD54HCT11F3A -55 to 125 14 Ld CERDIP

CD74HC11E -55 to 125 14 Ld PDIP

CD74HC11M -55 to 125 14 Ld SOIC

CD74HC11MT -55 to 125 14 Ld SOIC

CD74HC11M96 -55 to 125 14 Ld SOIC

CD74HCT11E -55 to 125 14 Ld PDIP

CD74HCT11M -55 to 125 14 Ld SOIC

CD74HCT11MT -55 to 125 14 Ld SOIC

CD74HCT11M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

GND

August 1997 - Revised September 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC11, CD74HC11,

CD54HCT11, CD74HCT11

High-Speed CMOS Logic

Triple 3-Input AND Gate

[

/Title

(

CD54

CT11

D74

C11,

D74

CT11

)

Sub-

ect

(

High

Summary of content (15 pages)

PAGE 1
[ /Title (CD54 HCT11 , CD74 HC11, CD74 HCT11 ) /Subject (High CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Data sheet acquired from Harris Semiconductor SCHS273E High-Speed CMOS Logic Triple 3-Input AND Gate August 1997 - Revised September 2003 Features Description • Buffered Inputs The ’HC11 and ’HCT11 logic gates utilize silicon gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits.
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CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Functional Diagram 1 14 2 13 1A 1B 2A 2B 2C 2Y GND VCC 1C 3 12 4 11 5 10 6 9 7 8 1Y 3C 3B 3A 3Y TRUTH TABLE INPUTS OUTPUT nA nB nC nY L L L L L L H L L H L L L H H L H L L L H L H L H H L L H H H H Logic Symbol nA nY nB nC 2
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CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . .
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CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 2 - 20 - 40 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.
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CD54HC11, CD74HC11, CD54HCT11, CD74HCT11 Switching Specifications Input tr, tf = 6ns PARAMETER Transition Times (Figure 1) Input Capacitance (Continued) SYMBOL TEST CONDITIONS tTLH, tTHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 75 - 95 - 110 ns 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC11M96 SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC11MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HCT11M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC11M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC11MT SOIC D 14 250 367.0 367.0 38.0 CD74HCT11M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HCT11MT SOIC D 14 250 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.