Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multivibrator Monostable 25 ns SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS142F

September 1997 - Revised October 2003

Features

• Overriding Reset Terminates Output Pulse

• Triggering From the Leading or Trailing Edge

• Q and

Q Buffered Outputs

• Separate Resets

• Wide Range of Output-Pulse Widths

• Schmitt Trigger on Both

A and B Inputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30%of V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC123, ’HCT123, CD74HC423 and CD74HCT423 are

dual monostable multivibrators with resets. They are all

retriggerable and differ only in that the 123 types can be

triggered by a negative to positive reset pulse; whereas the

423 types do not have this feature. An external resistor (R

)

and an external capacitor (C

) control the timing and the

accuracy for the circuit. Adjustment of Rx and C

provides a

wide range of output pulse widths from the Q and

terminals. Pulse triggering on the

A and B inputs occur at a

particular voltage level and is not related to the rise and fall

times of the trigger pulses.

Once triggered, the output pulse width may be extended by

retriggering inputs

A and B. The output pulse can be

terminated by a LOW level on the Reset (R) pin. Trailing

edge triggering (

A) and leading edge triggering (B) inputs

are provided for triggering from either edge of the input

pulse. If either Mono is not used each input on the unused

device (

A, B, and R) must be terminated high or low.

The minimum value of external resistance, Rx is typically

5kΩ. The minimum value external capacitance, CX, is 0pF.

The calculation for the pulse width is t

= 0.45 R

= 5V.

Ordering Information

PART NUMBER TEMP. RANGE (

C) PACKAGE

CD54HC123F3A -55 to 125 16 Ld CERDIP

CD54HCT123F3A -55 to 125 16 Ld CERDIP

CD74HC123E -55 to 125 16 Ld PDIP

CD74HC123M -55 to 125 16 Ld SOIC

CD74HC123MT -55 to 125 16 Ld SOIC

CD74HC123M96 -55 to 125 16 Ld SOIC

CD74HC123NSR -55 to 125 16 Ld SOP

CD74HC123PW -55 to 125 16 Ld TSSOP

CD74HC123PWR -55 to 125 16 Ld TSSOP

CD74HC123PWT -55 to 125 16 Ld TSSOP

CD74HC423E -55 to 125 16 Ld PDIP

CD74HC423M -55 to 125 16 Ld SOIC

CD74HC423MT -55 to 125 16 Ld SOIC

CD74HC423M96 -55 to 125 16 Ld SOIC

CD74HC423NSR -55 to 125 16 Ld SOP

CD74HCT123E -55 to 125 16 Ld PDIP

CD74HCT123M -55 to 125 16 Ld SOIC

CD74HCT123MT -55 to 125 16 Ld SOIC

CD74HCT123M96 -55 to 125 16 Ld SOIC

CD74HCT423E -55 to 125 16 Ld PDIP

CD74HCT423MT -55 to 125 16 Ld SOIC

CD74HCT423M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC123, CD54/74HCT123,

CD74HC423, CD74HCT423

High-Speed CMOS Logic Dual Retriggerable

Monostable Multivibrators with Resets

[ /Title

(CD74

HC123

D74

HCT12

CD74

HC423

D74

HCT42

/Sub-

ject

(High

Speed

Summary of content (23 pages)

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[ /Title (CD74 HC123 , CD74 HCT12 3, CD74 HC423 , CD74 HCT42 3) /Subject (High Speed CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Data sheet acquired from Harris Semiconductor SCHS142F September 1997 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Monostable Multivibrators with Resets Features Ordering Information • Overriding Reset Terminates Output Pulse PART NUMBER • Triggering From the Leading or Trailing Edge TEMP.
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Pinout Functional Diagram CD54HC123, CD54HCT123 (CERDIP) CD74HC123 (PDIP, SOIC, SOP, TSSOP) CD74HC423 (PDIP, SOIC, SOP) CD74HCT123, CD74HCT423 (PDIP, SOIC) TOP VIEW 1Cx 14 13 MONO 1 1Q 2 15 1RXCX 2R 1R 3 14 1CX 2A 1Q 4 13 1Q 2Q 5 12 2Q 3 11 5 9 2Q MONO 2 10 12 2B 2Q 2Cx 2RxCx 6 7 2Cx 9 2A GND 8 4 1B 1B 2 10 2B 1Q 1 1R 2RXCX 7 1RxCx 1A 16 VCC 11 2R VCC 15 1Cx 1A 1 2CX 6 1Rx TRUTH TABLE INPUTS A OUTPUTS B R Q Q
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . .
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER VCC (V) 25oC -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER R A and B Hold Time Reset Removal Time Retrigger Time Number -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tWL 2 100 - - 125 - - 150 - 150 ns 4.5 20 - - 25 - - 30 - 30 ns 6 17 - - 21 - - 26 - 26 ns 2 50 - - 65 - - 75 - 75 ns 4.
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Switching Specifications Input tr, tf = 6ns, RX = 10KΩ, CX = 0 -40oC TO 85oC 25oC PARAMETER -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNIT S 2 - - 300 - 375 - 450 ns 4.5 - - 60 - 75 - 90 ns CL = 15pF 5 - 25 - - - - - ns CL = 50pF 6 - - 51 - 64 - 76 ns CL = 50pF 2 - - 320 - 400 - 480 ns 4.
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CD54/74HC123, CD54/74HCT123, CD74HC423, CD74HCT423 Switching Specifications Input tr, tf = 6ns, RX = 10KΩ, CX = 0 (Continued) -40oC TO 85oC 25oC PARAMETER Pulse Width Match Between Circuits In the Same Package RX = 10KΩ, CX = 10pF Input Capacitance SYMBOL TEST CONDITIONS VCC (V) - - 5 CIN CL = 50pF - MIN - NOTE: 4. CPD is used to determine the dynamic power consumption, per multivibrator.
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Test Circuits and Waveforms A B = LOW A A = HIGH B = LOW A = HIGH B B R R VS VS tW tW tW VS Q VS Q tW tW tW FIGURE 1. OUTPUT PULSE CONTROL USING RESET INPUT (R) PULSE FOR 123 tW FIGURE 2. OUTPUT PULSE CONTROL USING RESET INPUT (R) FOR 423 A B tW B (R = HIGH) A trT Q VS tW tW tW NOTE: Output pulse control using retrigger pulse for 123 and 423. 8 6 4 2 0.9 EXTERNAL CAPACITANCE (CX) = 10nF 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC123M96 SOIC CD74HC123M96G4 CD74HC123NSR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 8.0 16.0 Q1 D 16 2500 330.0 16.8 6.5 10.3 2.1 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC123M96 SOIC D 16 2500 364.0 364.0 27.0 CD74HC123M96G4 SOIC D 16 2500 333.2 345.9 28.6 CD74HC123NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC123PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC123PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC423M96 SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.