Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply PDIP 16

Data sheet acquired from Harris Semiconductor

SCHS146F

Features

• Select One of Eight Data Outputs

- Active Low for CD74HC137 and CD74HCT137

- Active High for ’HC237 and CD74HCT237

• l/O Port or Memory Selector

• Two Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13ns at V

= 5V,

15pF, T

= 25

C (CD74HC237)

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30%, of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The CD74HC137, CD74HCT137, ’HC237, and

CD74HCT237 are high speed silicon gate CMOS decoders

well suited to memory address decoding or data routing

applications. Both circuits feature low power consumption

usually associated with CMOS circuitry, yet have speeds

comparable to low power Schottky TTL logic.

Both circuits have three binary select inputs (A0, A1 and A2)

that can be latched by an active High Latch Enable (LE)

signal to isolate the outputs from select-input changes. A

“Low” LE makes the output transparent to the input and the

circuit functions as a one-of-eight decoder. Two Output

Enable inputs (

and OE

) are provided to simplify

cascading and to facilitate demultiplexing. The

demultiplexing function is accomplished by using the A

inputs to select the desired output and using one of the

other Output Enable inputs as the data input while holding

the other Output Enable input in its active state. In the

CD74HC137 and CD74HCT137 the selected output is a

“Low”; in the ’HC237 and CD74HCT237 the selected output is

a “High”.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC237F3A -55 to 125 16 Ld CERDIP

CD74HC137E -55 to 125 16 Ld PDIP

CD74HC137PW -55 to 125 16 Ld TSSOP

CD74HC137PWR -55 to 125 16 Ld TSSOP

CD74HC137PWT -55 to 125 16 Ld TSSOP

CD74HC237E -55 to 125 16 Ld PDIP

CD74HC237M -55 to 125 16 Ld SOIC

CD74HC237MT -55 to 125 16 Ld SOIC

CD74HC237M96 -55 to 125 16 Ld SOIC

CD74HC237NSR -55 to 125 16 Ld SOP

CD74HC237PW -55 to 125 16 Ld TSSOP

CD74HC237PWR -55 to 125 16 Ld TSSOP

CD74HC237PWT -55 to 125 16 Ld TSSOP

CD74HCT137E -55 to 125 16 Ld PDIP

CD74HCT137MT -55 to 125 16 Ld SOIC

CD74HCT137M96 -55 to 125 16 Ld SOIC

CD74HCT237E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

March 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD74HC137, CD74HCT137,

CD54HC237, CD74HC237,

CD74HCT237

High-Speed CMOS Logic, 3- to 8-Line

Decoder/Demultiplexer with Address Latches

[ /Title

(CD74

HC137

D74

HCT13

CD74

HC237

D74

HCT23

/Sub-

ject

(High

Speed

Summary of content (22 pages)

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[ /Title (CD74 HC137 , CD74 HCT13 7, CD74 HC237 , CD74 HCT23 7) /Subject (High Speed Data sheet acquired from Harris Semiconductor SCHS146F March 1998 - Revised October 2003 CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 High-Speed CMOS Logic, 3- to 8-Line Decoder/Demultiplexer with Address Latches Features Both circuits have three binary select inputs (A0, A1 and A2) that can be latched by an active High Latch Enable (LE) signal to isolate the outputs from select-input changes.
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Pinout Functional Diagram CD54HC237 (CERDIP) CD74HC137 (PDIP, TSSOP) CD74HCT137 (PDIP, SOIC) CD74HC237 (PDIP, SOIC, SOP, TSSOP) CD74HCT237 (PDIP) TOP VIEW A0 A1 A2 A0 1 16 VCC A1 2 15 Y0 A3 3 14 Y1 LE 4 13 Y2 OE1 5 12 Y3 OE0 6 11 Y4 Y7 7 10 Y5 GND 8 9 Y6 HC/HCT HC/HCT 237 137 15 Y0 Y0 1 2 3-BIT LATCH 3 14 1 OF 8 DECODER 13 12 4 LE 11 10 OE1 OE0 5 9 6 7 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 GND = 8 VCC =
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Functional Block Diagram A0 15 LE 1 A0 Y0 A0 p 14 n Y1 LE LE p 13 Y2 n 12 LE Y3 A1 2 A1 A1 LATCH A0 11 Y4 10 3 A2 Y5 A2 A2 LATCH A2 9 Y6 LE 7 4 LE Y7 LE 5 OE1 6 OE0 3
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . .
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Prerequisite For Switching Specifications PARAMETER (Continued) 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tW 2 50 - - 65 - 75 - ns 4.5 10 - - 13 - 15 - ns 6 9 - - 1 - 13 - ns 4.5 10 - - 13 - 15 - ns LE Pulse Width HCT TYPES An to LE Setup Time tSU An to LE Hold Time CD74HCT137 tH 4.5 7 - - 9 - 11 - ns CD74HCT237 tH 4.
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Switching Specifications Input tr, tf = 6ns (Continued) PARAMETER TEST CONDITIONS SYMBOL HCT TYPES Propagation Delay An to any Y or Y Address to Output -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 38 - 48 - 57 ns tPLH, tPHL CL = 50pF tPLH, tPHL CL = 15pF 5 - 16 - - - - - ns OE0 to any Y (HC137) tPLH, tPHL CL = 50pF 4.
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CD74HC137, CD74HCT137, CD54HC237, CD74HC237, CD74HCT237 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (4) 25-Sep-2013 There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC137PWR TSSOP PW 16 CD74HC137PWT TSSOP PW CD74HC237M96 SOIC D CD74HC237NSR SO CD74HC237PWR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 5.6 1.6 8.0 12.0 Q1 2000 330.0 12.4 6.9 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC137PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC137PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC237M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC237NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC237PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC237PWT TSSOP PW 16 250 367.0 367.0 35.
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