Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register SMD 74 HC 165 Shift register Differential SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS156C

Features

• Buffered Inputs

• Asynchronous Parallel Load

• Complementary Outputs

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC165, CD54HCT165

(CERDIP)

CD74HC165, CD74HCT165

(PDIP, SOIC)

TOP VIEW

Description

The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift

registers with complementary serial outputs (Q

and Q

)

available from the last stage. When the parallel load (

PL)

input is LOW, parallel data from the D0 to D7 inputs are

loaded into the register asynchronously. When the

PL is

HIGH, data enters the register serially at the DS input and

shifts one place to the right (Q

→Q

, etc.) with each

positive-going clock transition. This feature allows parallel-

to-serial converter expansion by typing the Q

output to the

DS input of the succeeding device.

For predictable operation the LOW-to-HIGH transition of

should only take place while CP is HIGH. Also, CP an d

should be LOW before the LOW-to-HIGH transition of PL to

prevent shifting the data when

PL goes HIGH.

GND

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC165F3A -55 to 125 16 Ld CERDIP

CD54HCT165F3A -55 to 125 16 Ld CERDIP

CD74HC165E -55 to 125 16 Ld PDIP

CD74HC165M -55 to 125 16 Ld SOIC

CD74HC165MT -55 to 125 16 Ld SOIC

CD54HC165M96 -55 to 125 16 Ld SOIC

CD74HCT165E -55 to 125 16 Ld PDIP

CD74HCT165M -55 to 125 16 Ld SOIC

CD74HCT165MT -55 to 125 16 Ld SOIC

CD54HCT165M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC165, CD74HC165,

CD54HCT165, CD74HCT165

High-Speed CMOS Logic

8-Bit Parallel-In/Serial-Out Shift Register

[

/Title

(

CD74H

165,

D74H

T165)

Subject

(

High

peed

MOS

ogic 8-

it Par-

llel-

Summary of content (17 pages)

PAGE 1
[ /Title (CD74H C165, CD74H CT165) /Subject (High Speed CMOS Logic 8Bit Parallel- CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Data sheet acquired from Harris Semiconductor SCHS156C February 1998 - Revised October 2003 High-Speed CMOS Logic 8-Bit Parallel-In/Serial-Out Shift Register Features Description • Buffered Inputs The ’HC165 and ’HCT165 are 8-bit parallel or serial-in shift registers with complementary serial outputs (Q7 and Q7) available from the last stage.
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Functional Diagram D0 D1 D2 PARALLEL DATA INPUTS D3 11 12 13 14 3 D4 4 D5 D6 Q7 7 6 D7 DS 9 5 SERIAL OUTPUTS Q7 10 1 15 PL 2 GND = 8 VCC = 16 CE CP TRUTH TABLE INPUTS OPERATING MODE Parallel Load Serial Shift Hold Do Nothing H h l L X ↑ qn Qn REGISTER OUTPUTS PL CE CP DS D0 - D7 Q0 Q 1 - Q6 Q7 Q7 L X X X L L L-L L H L X X X H H H-H H L H L ↑ l X L q0 - q5 q6 q6 H L ↑ h X H q0 - q5 q6 q6 H H X X
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current per Output, IO For VO < -0.5V VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) ICC VCC or GND 0 High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - 8 - 80 - 160 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V VIH or VIL -0.
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Prerequisite For Switching Specifications (Continued) 25oC PARAMETER PL Pulse Width Set-up Time D0-D7 to PL Hold Time VCC (V) MIN MAX MIN MAX MIN MAX UNITS tWL 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS 2 - 165 205 250 ns 4.5 - 33 41 50 ns CL = 15pF 5 13 - - - ns CL = 50pF 6 - 28 35 43 ns CL = 50pF 2 - 175 220 265 ns 4.5 - 35 44 53 ns CL = 15pF 5 14 - - - ns CL = 50pF 6 - 30 37 45 ns CL = 50pF 2 - 150 190 225 ns 4.
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CD54HC165, CD74HC165, CD54HCT165, CD74HCT165 Test Circuits and Waveforms tr tf 90% 10% CP OR CE VS GND tW tW INPUT LEVEL 1/fMAX tPHL 90% Q7 OR Q7 PL tPLH tPHL tPLH VS 10% VS Q7 OR Q7 tTLH tTHL FIGURE 3. SERIAL-SHIFT MODE tr FIGURE 4. PARALLEL-LOAD MODE tf INPUT LEVEL 90% 10% INPUT D7 VALID INPUT LEVEL GND tPLH GND tSU VS tH INPUT LEVEL VS PL tTLH tTHL VS INPUTS D0-D7 tPHL 90% 10% Q7 OR Q7 VS GND FIGURE 5. PARALLEL-LOAD MODE FIGURE 6.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 18-Oct-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC165M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC165M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT165M96 SOIC D 16 2500 330.0 16.8 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 5-Oct-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC165M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC165M96 SOIC D 16 2500 367.0 367.0 38.0 CD74HCT165M96 SOIC D 16 2500 364.0 364.0 27.0 CD74HCT165M96G4 SOIC D 16 2500 333.2 345.9 28.
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