Datasheet

M54HC165
M74HC165
September 1993
8 BIT PISO SHIFT REGISTER
B1R
(Plastic Package)
ORDER CODES :
M54HC165F1R M74HC165M1R
M74HC165B1R M74HC165C1R
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
PIN CONNECTIONS (top view)
NC =
No Internal
Connection
.HIGH SPEED
t
PD
= 15 ns (TYP.) AT V
CC
=5V
.LOW POWER DISSIPATION
I
CC
=4µA (MAX.) AT T
A
=25°C
.OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
.BALANCEDPROPAGATION DELAYS
t
PLH
=t
PHL
.SYMMETRICAL OUTPUT IMPEDANCE
I
OL
= I
OH
= 4 mA (MIN.)
.HIGH NOISE IMMUNITY
V
NIH
=V
NIL
=28%V
CC
(MIN.)
.WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
.PIN AND FUNCTION COMPATIBLE
WITH 54/74LS165
DESCRIPTION
The M54/74HC165 is a high speed CMOS 8 BIT
PISO SHIFT REGISTER fabricated in silicon gate
C
2
MOS technology. It has the same high speed
performance of LSTTL combined with true CMOS
low power consumption.
It achives the high speed operation similar to
equivalent LSTTL while maintaining the CMOS low
power dissipation.
This device contains eight clocked master slave RS
flip-flops connected as a shift register, with auxiliary
gating to provide over-riding asynchronous parallel
entry. Parallel data entres when the shift/load input
is low. The parallel data can change while shift/load
is low, provided that the recommended set-up and
hold times are observed. For clocked operation,
shift/load must be high. The two clock input perform
identically; one can be used as a clock inhibit by
applying a high signal; to permit this operation
clocking is accomplished through a 2 input nor gate.
To avoid double clocking, however, the inhibit signal
should only go high while the clock is high.
Otherwise the rising inhibit signal will cause the
same response as rising clock edge.
All inputs are equipped with protection circuits
against static discharge and transient excess
voltage.
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