Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Three-state, Non-inverting SOIC 16

Data sheet acquired from Harris Semiconductor

SCHS158E

Features

• Three-State Buffered Outputs

• Gated Input and Output Enables

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC173, CD54HCT173

(CERDIP)

CD74HC173

(PDIP, SOIC, SOP, TSSOP)

CD74HCT173

(PDIP, SOIC)

TOP VIEW

Description

The ’HC173 and ’HCT173 high speed three-state quad D-

type ﬂip-ﬂops are fabricated with silicon gate CMOS technol-

ogy. They possess the low power consumption of standard

CMOS Integrated circuits, and can operate at speeds com-

parable to the equivalent low power Schottky devices. The

buffered outputs can drive 15 LSTTL loads. The large output

drive capability and three-state feature make these parts ide-

ally suited for interfacing with bus lines in bus oriented sys-

tems.

The four D-type ﬂip-ﬂops operate synchronously from a com-

mon clock. The outputs are in the three-state mode when

either of the two output disable pins are at the logic “1” level.

The input ENABLES allow the ﬂip-ﬂops to remain in their

present states without having to disrupt the clock If either of

the 2 input ENABLES are taken to a logic “1” level, the Q

outputs are fed back to the inputs, forcing the ﬂip-ﬂops to

remain in the same state. Reset is enabled by taking the

MASTER RESET (MR) input to a logic “1” level. The data

outputs change state on the positive going edge of the clock.

The ’HCT173 logic family is functionally, as well as pin com-

patible with the standard LS logic family

OE2

GND

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC173F3A -55 to 125 16 Ld CERDIP

CD54HCT173F3A -55 to 125 16 Ld CERDIP

CD74HC173E -55 to 125 16 Ld PDIP

CD74HC173M -55 to 125 16 Ld SOIC

CD74HC173MT -55 to 125 16 Ld SOIC

CD74HC173M96 -55 to 125 16 Ld SOIC

CD74HC173NSR -55 to 125 16 Ld SOP

CD74HC173PW -55 to 125 16 Ld TSSOP

CD74HC173PWR -55 to 125 16 Ld TSSOP

CD74HC173PWT -55 to 125 16 Ld TSSOP

CD74HCT173E -55 to 125 16 Ld PDIP

CD74HCT173M -55 to 125 16 Ld SOIC

CD74HCT173MT -55 to 125 16 Ld SOIC

CD74HCT173M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC173, CD74HC173,

CD54HCT173, CD74HCT173

High-Speed CMOS Logic

Quad D-Type Flip-Flop, Three-State

[

/Title

(

CD74H

173,

D74H

T173)

Subject

(

High

peed

MOS

ogic

uad D-

ype

Summary of content (22 pages)

PAGE 1
[ /Title (CD74H C173, CD74H CT173) /Subject (High Speed CMOS Logic Quad DType CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Data sheet acquired from Harris Semiconductor SCHS158E High-Speed CMOS Logic Quad D-Type Flip-Flop, Three-State February 1998 - Revised October 2003 Features Description • Three-State Buffered Outputs The ’HC173 and ’HCT173 high speed three-state quad Dtype flip-flops are fabricated with silicon gate CMOS technology.
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Functional Diagram E1 E2 10 D0 D1 9 14 3 Q0 13 4 Q1 12 D2 5 Q2 11 D3 6 Q3 7 CP 15 MR 1 2 OE1 OE2 TRUTH TABLE INPUTS DATA ENABLE DATA OUTPUT MR CP E1 E2 D Qn H X X X X L L L X X X Q0 L ↑ H X X Q0 L ↑ X H X Q0 L ↑ L L L L L ↑ L L H H H= High Voltage Level L = Low Voltage Level X= Irrelevant ↑= Transition from Low to High Level Q0= Level Before the Indicated Steady-State Input Conditions Were Established NO
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Logic Diagram 9 E1 10 E2 D Q 14 VCC P D0 3 Q0 7 CP CP Q N R 15 MR 1 OE1 2 OE2 13 4 D1 12 D2 11 3 CIRCUITS IDENTICAL TO ABOVE CIRCUIT IN DASHED ENCLOSURE D3 5 Q1 Q2 6 Q3 3
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IOZ VIL or VIH - High Level Input Voltage VIH - Low Level Input Voltage VIL High Level Output Voltage CMOS Loads VOH PARAMETER Three-State Leakage Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.5 - ±0.5 - ±10 µA - 4.5 to 5.5 2 - - 2 - 2 - V - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Switching Specifications PARAMETER Input tr, tf = 6ns SYMBOL TEST CONDITIONS tPLH, tPHL CL = 50pF 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS HC TYPES Propagation Delay, Clock to Output Propagation Delay, MR to Output Propagation Delay Output Enable to Q (Figure 6) Output Transition Times Maximum Clock Frequency tPHL tPLZ, tPHZ tPZL, tPZH tTLH, tTHL fMAX 2 - 200 250 300 ns 4.
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Prerequisite For Switching Specifications 25oC PARAMETER -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS fMAX 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 24 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 60 - 75 - 90 - ns 4.
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CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% tf = 6ns tr = 6ns GND tTLH 90% INVERTING OUTPUT tPHL FIGURE 3. HC AND HCU TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tPLH FIGURE 4. HCT TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC tfCL 10% tTLH 1.
PAGE 9
CD54HC173, CD74HC173, CD54HCT173, CD74HCT173 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE 90% 50% 10% OUTPUTS ENABLED 2.7 1.3 OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com Orderable Device 25-Sep-2013 Status (1) CD74HCT173MTG4 ACTIVE Package Type Package Pins Package Drawing Qty SOIC D 16 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-1-260C-UNLIM (4/5) -55 to 125 HCT173M (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC173M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC173PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC173PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC173M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC173PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC173PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT173M96 SOIC D 16 2500 333.2 345.9 28.
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