Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Flip-Flop Master rest Non-inverting SOIC 16

Data sheet acquired from Harris Semiconductor

SCHS159C

Features

• Buffered Positive Edge Triggered Clock

• Asynchronous Common Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC174 and ’HCT174 are edge triggered flip-flops which

utilize silicon gate CMOS circuitry to implement D-type flip-

flops. They possess low power and speeds comparable to low

power Schottky TTL circuits. The devices contain six master-

slave ﬂip-ﬂops with a common clock and common reset.

Data on the D input having the speciﬁed setup and hold

times is transferred to the Q output on the low to high

transition of the CLOCK input. The

MR input, when low, sets

all outputs to a low state.

Each output can drive ten low power Schottky TTL

equivalent loads. The ’HCT174 is functional as well as, pin

compatible to the ’LS174.

Pinout

CD54HC174, CD54HCT174

(CERDIP)

CD74HC174, CD74HCT174

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC174F3A -55 to 125 16 Ld CERDIP

CD54HCT174F3A -55 to 125 16 Ld CERDIP

CD74HC174E -55 to 125 16 Ld PDIP

CD74HC174M -55 to 125 16 Ld SOIC

CD74HC174MT -55 to 125 16 Ld SOIC

CD74HC174M96 -55 to 125 16 Ld SOIC

CD74HCT174E -55 to 125 16 Ld PDIP

CD74HCT174M -55 to 125 16 Ld SOIC

CD74HCT174MT -55 to 125 16 Ld SOIC

CD74HCT174M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel of

250.

GND

August 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC174, CD74HC174,

CD54HCT174, CD74HCT174

High-Speed CMOS Logic

Hex D-Type Flip-Flop with Reset

[

/Title

(

CD74

C174

D74

CT17

)

Sub-

ect

(

High

peed

MOS

ogic

ex D-

ype

lip-

lop

Summary of content (16 pages)

PAGE 1
[ /Title (CD74 HC174 , CD74 HCT17 4) /Subject (High Speed CMOS Logic Hex DType FlipFlop CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Data sheet acquired from Harris Semiconductor SCHS159C High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset August 1997 - Revised October 2003 Features times is transferred to the Q output on the low to high transition of the CLOCK input. The MR input, when low, sets all outputs to a low state.
PAGE 2
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Functional Diagram CP CP D R D0 Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 MR TRUTH TABLE INPUTS OUTPUT RESET (MR) CLOCK CP DATA Dn Qn L X X L H ↑ H H H ↑ L L H L X Q0 H = High Voltage Level, L = Low Voltage Level, X = Irrelevant, ↑ = Transition from Low to High Level, Q0 = Level Before the Indicated Steady-State Input Conditions Were Established Logic Diagram 3 (4, 6, 11, 13, 14) Dn D CL CL p p n n CL CL CL CL p p n n
PAGE 3
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . .
PAGE 4
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO +85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
PAGE 5
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Prerequisite For Switching Function PARAMETER SYMBOL Setup Time, Data to Clock (Continued) TEST CONDITIONS VCC (V) tSU Hold Time, Data to Clock Removal Time, MR to Clock Clock Frequency MAX MIN MAX MIN MAX UNITS 2 60 - 75 - 90 - ns 4.5 12 - 15 - 18 - ns 6 10 - 13 - 15 - ns 2 5 - 5 - 5 - ns 4.5 5 - 5 - 5 - ns 6 5 - 5 - 5 - ns 2 5 - 5 - 5 - ns 4.
PAGE 6
CD54HC174, CD74HC174, CD54HCT174, CD74HCT174 Switching Specifications PARAMETER Input tr, tf = 6ns (Continued) SYMBOL TEST CONDITIONS tPLH, tPHL 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) TYP MAX MAX MAX UNITS CL = 50pF 4.5 - 40 50 60 ns CL = 15pF 5 17 - - - ns CL = 50pF 4.5 - 44 55 66 ns CL = 15pF 5 18 - - - ns CL = 50pF 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC174M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT174M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC174M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT174M96 SOIC D 16 2500 333.2 345.9 28.
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