Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Counter, Tenth 74HC Positive slope 24 MHz TSSOP 16

Data sheet acquired from Harris Semiconductor

SCHS163F

Features

• Synchronous Counting and Asynchronous

• Two Outputs for N-Bit Cascading

• Look-Ahead Carry for High-Speed Counting

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC192, ’HC193 and ’HCT193 are asynchronously

presettable BCD Decade and Binary Up/Down synchronous

counters, respectively.

Pinout

CD54HC192, CD54HC193, CD54HCT193 (CERDIP)

CD74HC192 (PDIP, SOP, TSSOP)

CD74HC193 (PDIP, SOIC)

CD74HCT193 (PDIP)

TOP VIEW

Presetting the counter to the number on the preset data inputs

(P0-P3) is accomplished by a LOW asynchronous parallel

load input (

PL). The counter is incremented on the low-to-high

transition of the Clock-Up input (and a high level on the Clock-

Down input) and decremented on the low to high transition of

the Clock-Down input (and a high level on the Clock-up input).

A high level on the MR input overrides any other input to clear

the counter to its zero state. The Terminal Count up (carry)

goes low half a clock period before the zero count is reached

and returns to a high level at the zero count. The Terminal

Count Down (borrow) in the count down mode likewise goes

low half a clock period before the maximum count (9 in the

192 and 15 in the 193) and returns to high at the maximum

count. Cascading is effected by connecting the carry and

borrow outputs of a less significant counter to the Clock-Up

and Clock-Down inputs, respectively, of the next most

significant counter.

If a decade counter is preset to an illegal state or assumes an

illegal state when power is applied, it will return to the normal

sequence in one count as shown in state diagram.

CPD

CPU

GND

TCD

TCU

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC192F3A -55 to 125 16 Ld CERDIP

CD54HC193F3A -55 to 125 16 Ld CERDIP

CD54HCT193F3A -55 to 125 16 Ld CERDIP

CD74HC192E -55 to 125 16 Ld PDIP

CD74HC192NSR -55 to 125 16 Ld SOP

CD74HC192PW -55 to 125 16 Ld TSSOP

CD74HC192PWR -55 to 125 16 Ld TSSOP

CD74HC192PWT -55 to 125 16 Ld TSSOP

CD74HC193E -55 to 125 16 Ld PDIP

CD74HC193M -55 to 125 16 Ld SOIC

CD74HC193MT -55 to 125 16 Ld SOIC

CD74HC193M96 -55 to 125 16 Ld SOIC

CD74HCT193E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

September 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC192,

CD54/74HC193, CD54/74HCT193

High-Speed CMOS Logic

Presettable Synchronous 4-Bit Up/Down Counters

[

/Title

(

CD74

C192

D74

C193

D74

CT19

)

Sub-

ect

(

High

peed

MOS

ogic

reset-

Summary of content (23 pages)

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[ /Title (CD74 HC192 , CD74 HC193 , CD74 HCT19 3) /Subject (High Speed CMOS Logic Preset- CD54/74HC192, CD54/74HC193, CD54/74HCT193 Data sheet acquired from Harris Semiconductor SCHS163F September 1997 - Revised October 2003 High-Speed CMOS Logic Presettable Synchronous 4-Bit Up/Down Counters Features Presetting the counter to the number on the preset data inputs (P0-P3) is accomplished by a LOW asynchronous parallel load input (PL).
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Functional Diagram BCD/BINARY PRESET P0 15 ASYN.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . .
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL HC TYPES Pulse Width tW CPU, CPD 192 tW CPU, CPD 193 PL tW MR tW Set-up Time tSU Pn to PL Hold Time tH Pn to PL Hold Time tH CPD to CPU or CPU to CPD Recovery Time tREC PL to CPU, CPD MR to CPU, CPD tREC Maximum Frequency fMAX CPU, CPD 192 fMAX CPU, CPD 193 HCT TYPES Pulse Width tW CPU, CPD 192 CPU, CPD tW 193 25oC -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX M
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Prerequisite For Switching Specifications PARAMETER SYMBOL PL VCC (V) tW MR Hold Time Hold Time MR to CPU, CPD - - - - ns - 24 - ns 6 - - - - - - - ns 2 - - - - - - - ns 4.5 20 - - 25 - 30 - ns 6 - - - - - - - ns 2 - - - - - - - ns 4.5 15 - - 19 - 22 - ns 6 - - - - - - - ns 2 - - - - - - - ns 4.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Switching Specifications PARAMETER CPD to Qn PL to Qn MR to Qn Transition Time Input tr, tf = 6ns (Continued) SYMBOL tPLH, tPHL CL = 50pF 2 CL = 50pF 4.5 CL = 15pF 5 - CL = 50pF 6 - CL = 50pF 2 - CL = 50pF 4.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms MASTER RESET ASYNCHRONOUS PARALLEL LOAD P0 PRESET DATA P1 P2 P3 SEQUENCES: 1. RESET OUTPUTS TO ZERO. CLOCK UP 2. LOAD (PRESET) TO BCD SEVEN. 3. COUNT UP TO EIGHT, NINE, CLOCK DOWN TERMINAL COUNT UP, ZERO, ONE AND TWO. Q0 4. COUNT DOWN TO ONE, ZERO, TERMINAL COUNT DOWN, NINE, Q1 EIGHT AND SEVEN. OUTPUTS Q2 Q3 TERMINAL COUNT UP TERMINAL COUNT DOWN 0 8 7 RESET PRESET 9 0 1 COUNT UP 2 1 0 9 8 7 COUNT DOWN FIGURE 1.
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CD54/74HC192, CD54/74HC193, CD54/74HCT193 Test Circuits and Waveforms (Continued) MASTER RESET ASYNCHRONOUS PARALLEL LOAD P0 P1 PRESET DATA P2 P3 SEQUENCES: 1. RESET OUTPUTS TO ZERO. 2. LOAD (PRESET) TO BINARY THIRTEEN. CLOCK UP 3. COUNT UP TO FOURTEEN, CLOCK DOWN FIFTEEN, TERMINAL COUNT UP, ZERO, ONE AND TWO. 4. COUNT DOWN TO ONE, ZERO, Q0 TERMINAL COUNT DOWN, FIFTEEN, FOURTEEN AND Q1 THIRTEEN. OUTPUTS Q2 Q3 TERMINAL COUNT UP TERMINAL COUNT DOWN 0 NOTES: 1.
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Test Circuits and Waveforms (Continued) VS Pn tSU(H) PL Qn tH tSU(L) VS INPUT LEVEL tH VS INPUT LEVEL Q=p Q=p FIGURE 7. SET-UP AND HOLD TIMES DATA TO PARALLEL LOAD (PL) DATA INPUT UP CLOCK DOWN CLOCK ASYNCHRONOUS, PARALLEL LOAD P0 P1 P2 P3 TCU CPU TCD CPD PL MR Q0 Q1 Q2 Q3 P0 P1 P2 P3 TCU CPU TCD CPD PL MR Q0 Q1 Q2 Q3 BORROW CARRY RESET OUTPUT FIGURE 8.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC192NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC192PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC192PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC192NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC192PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC192PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HC193M96 SOIC D 16 2500 333.2 345.9 28.
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