Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Register, Bidirectional Push pull TSSOP 16

Data sheet acquired from Harris Semiconductor

SCHS164G

Features

• Four Operating Modes

- Shift Right, Shift Left, Hold and Reset

• Synchronous Parallel or Serial Operation

• Typical f

MAX

= 60MHz at V

= 5V, C

= 15pF,

= 25

• Asynchronous Master Reset

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC194 (CERDIP)

CD74HC194 (PDIP, SOIC, SOP, TSSOP)

CD74HCT194 (PDIP)

TOP VIEW

Description

The ’HC194 and CD74HCT194 are 4-bit shift registers with

Asynchronous Master Reset (

MR). In the parallel mode (S0

and S1 are high), data is loaded into the associated ﬂip-ﬂop

and appears at the output after the positive transition of the

clock input (CP). During parallel loading serial data ﬂow is

inhibited. Shift left and shift right are accomplished

synchronously on the positive clock edge with serial data

entered at the shift left (DSL) serial input for the shift left

mode, and at the shift right (DSR) serial input for the shift

right mode. Clearing the register is accomplished by a Low

applied to the Master Reset (

MR) pin.

DSR

GND

DSL

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC194F3A -55 to 125 16 Ld CERDIP

CD74HC194E -55 to 125 16 Ld PDIP

CD74HC194M -55 to 125 16 Ld SOIC

CD74HC194MT -55 to 125 16 Ld SOIC

CD74HC194M96 -55 to 125 16 Ld SOIC

CD74HC194NSR -55 to 125 16 Ld SOP

CD74HC194PW -55 to 125 16 Ld TSSOP

CD74HC194PWR -55 to 125 16 Ld TSSOP

CD74HC194PWT -55 to 125 16 Ld TSSOP

CD74HCT194E -55 to 125 16 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

September 1997 - Revised May 2006

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC194, CD74HC194,

CD74HCT194

High-Speed CMOS Logic

4-Bit Bidirectional Universal Shift Register

[

/Title

(

CD74

C194,

D74H

T194)

Sub-

ect

(

High-

peed

MOS

ogic

-Bit

Summary of content (18 pages)

PAGE 1
[ /Title (CD74 HC194, CD74H CT194) /Subject (HighSpeed CMOS Logic 4-Bit CD54HC194, CD74HC194, CD74HCT194 Data sheet acquired from Harris Semiconductor SCHS164G September 1997 - Revised May 2006 High-Speed CMOS Logic 4-Bit Bidirectional Universal Shift Register Features Description • Four Operating Modes - Shift Right, Shift Left, Hold and Reset • Synchronous Parallel or Serial Operation • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . .
PAGE 2
CD54HC194, CD74HC194, CD74HCT194 Functional Diagram D0 D1 D2 D3 DSL 3 15 4 14 5 13 6 12 2 7 9 10 1 DSR 11 Q0 Q1 Q2 Q3 GND = 8 VCC = 16 S0 S1 MR CP TRUTH TABLE INPUTS OPERATING MODE OUTPUT CP MR S1 S0 DSR DSL Dn Q0 Q1 Q2 Q3 Reset (Clear) X L X X X X X L L L L Hold (Do Nothing) X H l l X X X q0 q1 q2 q3 Shift Left ↑ H h l X l X q1 q2 q3 L ↑ H h l X h X q1 q2 q3 H ↑ H l h l X X L q0 q1 q2 ↑ H l h h X X H q0 q1 q2
PAGE 3
CD54HC194, CD74HC194, CD74HCT194 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
PAGE 4
CD54HC194, CD74HC194, CD74HCT194 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) II VCC or GND - ICC VCC or GND High Level Input Voltage VIH Low Level Input Voltage High Level Output Voltage CMOS Loads PARAMETER Input Leakage Current Quiescent Device Current 25oC IO (mA) VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 6 - - ±0.1 - ±1 - ±1 µA 0 6 - - 8 - 80 - 160 µA - - 4.5 to 5.
PAGE 5
CD54HC194, CD74HC194, CD74HCT194 Prerequisite For Switching Function 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS 2 6 - 5 - 4 - MHz 4.5 30 - 24 - 20 - MHz 6 35 - 28 - 23 - MHz 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns 2 70 - 90 - 105 - ns 4.
PAGE 6
Prerequisite For Switching Function (Continued) 25oC PARAMETER SYMBOL TEST CONDITIONS VCC (V) -40oC TO 85oC -55oC TO 125oC MIN MAX MIN MAX MIN MAX UNITS Set-up Time S1, S0 to Clock (Figure 4) tSU - 4.5 20 - 25 - 30 - ns Set-up Time DSL, DSR to Clock (Figure 4) tSU - 4.5 14 - 18 - 21 - ns Hold Time S1, S0 to Clock (Figure 4) tH - 4.5 0 - 0 - 0 - ns Hold Time Data to Clock (Figure 3) tH - 4.
PAGE 7
Test Circuits and Waveforms tr INPUT LEVEL CP 10% tf 90% VS VS 10% MR VS INPUT LEVEL VS GND tW tW tPLH tPHL 90% VS 10% tTLH VS tTHL tPHL VALID S OR DS CP VS INPUT LEVEL VS GND tH GND FIGURE 2. MASTER RESET PREREQUISITE TIMES AND PROPAGATION DELAYS INPUT LEVEL tSU INPUT LEVEL VS VALID VS tREM Q FIGURE 1. CLOCK PREREQUISITE TIMES AND PROPAGATION AND OUTPUT TRANSITION TIMES DATA GND VS CP Q VS tSU INPUT LEVEL CP GND FIGURE 3.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PAGE 11
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC194M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC194PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 CD74HC194PWT TSSOP PW 16 250 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC194M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC194PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC194PWT TSSOP PW 16 250 367.0 367.0 35.
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