Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS165E
Features
• Asynchronous Master Reset
•J,
K, (D) Inputs to First Stage
• Fully Synchronous Serial or Parallel Data Transfer
• Shift Right and Parallel Load Capability
• Complementary Output From Last Stage
• Buffered Inputs
• Typical f
MAX
= 50MHz at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30%of V
CC
at
V
CC
= 5V
PInout
CD54HC195
(CERDIP)
CD74HC195
(PDIP, SOIC, SOP, TSSOP)
TOP VIEW
Description
The device is useful in a wide variety of shifting, counting
and storage applications. It performs serial, parallel, serial to
parallel, or parallel to serial data transfers at very high
speeds.
The two modes of operation, shift right (Q
0
-Q
1
) and parallel
load, are controlled by the state of the Parallel Enable (
PE)
input. Serial data enters the first flip-flop (Q
0
) via the J and K
inputs when the
PE input is high, and is shifted one bit in the
direction Q
0
-Q
1
-Q
2
-Q
3
following each Low to High clock
transition. The J and
K inputs provide the flexibility of the JK-
type input for special applications and by tying the two pins
together, the simple D-type input for general applications.
The device appears as four common-clocked D flip-flops
when the
PE input is Low. After the Low to High clock
transition, data on the parallel inputs (D0-D3) is transferred
to the respective Q
0
-Q
3
outputs. Shift left operation (Q
3
-Q
2
)
can be achieved by tying the Q
n
outputs to the Dn-1 inputs
and holding the
PE input low.
All parallel and serial data transfers are synchronous, occurring
after each Low to High clock transition. The ’HC195 series
utilizes edge triggering; therefore, there is no restriction on the
activity of the J,
K, Pn and PE inputs for logic operations, other
than set-up and hold time requirements. A Low on the
asynchronous Master Reset (
MR) input sets all Q outputs Low,
independent of any other input condition.
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
MR
J
K
D0
D1
D2
GND
D3
V
CC
Q
1
Q
2
Q
3
Q
3
CP
PE
Q
0
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC195F3A -55 to 125 16 Ld CERDIP
CD74HC195E -55 to 125 16 Ld PDIP
CD74HC195M -55 to 125 16 Ld SOIC
CD74HC195NSR -55 to 125 16 Ld SOP
CD74HC195PW -55 to 125 16 Ld TSSOP
CD74HC195PWR -55 to 125 16 Ld TSSOP
CD74HC195PWT -55 to 125 16 Ld TSSOP
NOTE: When ordering, use the entire part number. The suffix R
denotes tape and reel. The suffix T denotes a small-quantity reel of
250.
September 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC195, CD74HC195
High-Speed CMOS Logic
4-Bit Parallel Access Register
[
/Title
(
CD74
H
C195
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
4
-Bit
P
aral-
l
el
A
ccess
R
egis-
t
er)
/
Autho