Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Demultiplexer, decoder Decoder/demultiplexer Single supply SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS147I

Features

• Select One Of Eight Data Outputs

Active Low for 138, Active High for 238

• l/O Port or Memory Selector

• Three Enable Inputs to Simplify Cascading

• Typical Propagation Delay of 13 ns at V

= 5 V,

= 15 pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2 V to 6 V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5 V

• HCT Types

- 4.5-V to 5.5-V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8 V (Max), V

= 2 V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC138, ’HC238, ’HCT138, and ’HCT238 are high-speed

silicon-gate CMOS decoders well suited to memory address

decoding or data-routing applications. Both circuits feature

low power consumption usually associated with CMOS

circuitry, yet have speeds comparable to low-power Schottky

TTL logic. Both circuits have three binary select inputs (A0,

A1, and A2). If the device is enabled, these inputs determine

which one of the eight normally high outputs of the

HC/HCT138 series go low or which of the normally low

outputs of the HC/HCT238 series go high.

Two active low and one active high enables (

E1, E2, and E3)

are provided to ease the cascading of decoders. The

decoder’s eight outputs can drive ten low-power Schottky

TTL equivalent loads.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC138F3A -55 to 125 16 Ld CERDIP

CD54HC238F3A -55 to 125 16 Ld CERDIP

CD54HCT138F3A -55 to 125 16 Ld CERDIP

CD54HCT238F3A -55 to 125 16 Ld CERDIP

CD74HC138E -55 to 125 16 Ld PDIP

CD74HC138M -55 to 125 16 Ld SOIC

CD74HC138MT -55 to 125 16 Ld SOIC

CD74HC138M96 -55 to 125 16 Ld SOIC

CD74HC238E -55 to 125 16 Ld PDIP

CD74HC238M -55 to 125 16 Ld SOIC

CD74HC238MT -55 to 125 16 Ld SOIC

CD74HC238M96 -55 to 125 16 Ld SOIC

CD74HC238NSR -55 to 125 16 Ld SOP

CD74HC238PW -55 to 125 16 Ld TSSOP

CD74HC238PWR -55 to 125 16 Ld TSSOP

CD74HC238PWT -55 to 125 16 Ld TSSOP

CD74HCT138E -55 to 125 16 Ld PDIP

CD74HCT138M -55 to 125 16 Ld SOIC

CD74HCT138MT -55 to 125 16 Ld SOIC

CD74HCT138M96 -55 to 125 16 Ld SOIC

CD74HCT238E -55 to 125 16 Ld PDIP

CD74HCT238M -55 to 125 16 Ld SOIC

CD74HCT238M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

October 1997 - Revised August 2004

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC138, CD54/74HCT138,

CD54/74HC238, CD54/74HCT238

High-Speed CMOS Logic 3- to 8-Line Decoder/

Demultiplexer Inverting and Noninverting

[ /Title

(CD74

HC138

D74

HCT13

CD74

HC238

D74

HCT23

/Sub-

ject

(High

Speed

Summary of content (20 pages)

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[ /Title (CD74 HC138 , CD74 HCT13 8, CD74 HC238 , CD74 HCT23 8) /Subject (High Speed CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Data sheet acquired from Harris Semiconductor SCHS147I October 1997 - Revised August 2004 High-Speed CMOS Logic 3- to 8-Line Decoder/ Demultiplexer Inverting and Noninverting Features Ordering Information • Select One Of Eight Data Outputs Active Low for 138, Active High for 238 TEMP.
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Pinout Functional Diagram HC/HCT HC/HCT 238 138 CD54HC138, CD54HCT138, CD54HC238, CD54HCT238 (CERDIP) CD74HC138, CD74HCT138, CD74HCT238 (PDIP, SOIC) CD74HC238 (PDIP, SOIC, SOP, TSSOP) TOP VIEW A0 1 15 2 14 3 13 A1 A2 Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 12 A0 1 16 VCC A1 2 15 Y0 (Y0) A2 3 14 Y1 (Y1) E1 4 13 Y2 (Y2) E2 5 12 Y3 (Y3) E3 6 11 Y4 (Y4) (Y7) Y7 7 10 Y5 (Y5) GND 8 9 Y6 (Y6) 4 11 5 10 6
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . .
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.
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CD54/74HC138, CD54/74HCT138, CD54/74HC238, CD54/74HCT238 Switching Specifications Input tr, tf = 6ns PARAMETER TEST CONDITIONS SYMBOL Enable to Output HC/HCT138 (Continued) tPLH, tPHL CL = 50pF Output Transition Time (Figure 1) tTLH, tTHL CL = 50pF Power Dissipation Capacitance (Notes 3, 4) CPD Input Capacitance CIN CL = 15pF - -40oC TO 85oC 25oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 150 - 190 - 265 ns 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC138M96 SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) 8.0 16.0 Q1 D 16 2500 330.0 16.4 6.5 10.3 2.1 W Pin1 (mm) Quadrant CD74HC238M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC238NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC138M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC238M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC238NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC238PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC238PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT138M96 SOIC D 16 2500 333.2 345.9 28.
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