Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Latch D type, Addressable Standard PDIP 16

Data sheet acquired from Harris Semiconductor

SCHS173C

Features

• Buffered Inputs and Outputs

• Four Operating Modes

• Typical Propagation Delay of 15ns at V

= 5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC259 and ’HCT259 Addressable Latch features the

low-power consumption associated with CMOS circuitry and

has speeds comparable to low-power Schottky.

This latches three active modes and one reset mode. When

both the Latch Enable (

LE) and Master Reset (MR) inputs are

low (8-line Demultiplexer mode) the output of the addressed

latch follows the Data input and all other outputs are forced

low. When both

MR and LE are high (Memory Mode), all

outputs are isolated from the Data input, i.e., all latches hold

the last data presented before the

LE transition from low to

high. A condition of

LE low and MR high (Addressable Latch

mode) allows the addressed latch’s output to follow the data

input; all other latches are unaffected. The Reset mode (all

outputs low) results when

LE is high and MR is low.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC259F3A -55 to 125 16 Ld CERDIP

CD54HCT259F3A -55 to 125 16 Ld CERDIP

CD74HC259E -55 to 125 16 Ld PDIP

CD74HC259M -55 to 125 16 Ld SOIC

CD74HC259MT -55 to 125 16 Ld SOIC

CD74HC259M96 -55 to 125 16 Ld SOIC

CD74HCT259E -55 to 125 16 Ld PDIP

CD74HCT259M -55 to 125 16 Ld SOIC

CD74HCT259MT -55 to 125 16 Ld SOIC

CD74HCT259M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel. The sufﬁx T denotes a small-quantity reel

of 250.

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC259, CD74HC259,

CD54HCT259, CD74HCT259

High-Speed CMOS Logic

8-Bit Addressable Latch

[ /Title

(CD74

HC259

D74

HCT25

/Sub-

ject

(High

Speed

CMOS

Logic

8-Bit

Addres

sable

Latch)

Summary of content (18 pages)

PAGE 1
[ /Title (CD74 HC259 , CD74 HCT25 9) /Subject (High Speed CMOS Logic 8-Bit Addres sable Latch) CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Data sheet acquired from Harris Semiconductor SCHS173C High-Speed CMOS Logic 8-Bit Addressable Latch November 1997 - Revised October 2003 Features Description • Buffered Inputs and Outputs The ’HC259 and ’HCT259 Addressable Latch features the low-power consumption associated with CMOS circuitry and has speeds comparable to low-power Schottky.
PAGE 2
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Pinout CD54HC259, CD54HCT259 (CERDIP) CD74HC259, CD74HCT259 (PDIP, SOIC) TOP VIEW A0 1 16 VCC A1 2 15 MR A2 3 14 LE Q0 4 13 D Q1 5 12 Q7 Q2 6 11 Q6 Q3 7 10 Q5 GND 8 9 Q4 Functional Diagram 4 1 5 A0 2 A1 A2 LE 8 LATCHES 1-OF-8 DECODER 6 7 3 9 10 14 11 15 MR 12 13 D Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND = 8 VCC = 16 TRUTH TABLE INPUTS MR LE OUTPUT OF ADDRESS LATCH H L D LATCH SELECTION TABLE SELECT INPUTS EACH OTHER OUTPUT Qio FUNCTION
PAGE 3
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Drain Current, per Output, IO For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) ICC VCC or GND 0 6 - - 8 - 80 - 160 µA High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER MR Setup Time -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tWL 2 70 - - 90 - - 105 - - ns 4.5 14 - - 18 - - 21 - - ns 6 12 - - 15 - - 18 - - ns 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 0 - - 0 - - 0 - - ns 4.
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC PARAMETER A to Q MR to Q Output Transition Time Power Dissipation Capacitance (Notes 3, 4) Input Capacitance -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPHL CL = 50pF 2 - - 185 - 230 - 280 ns 4.
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CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits and Waveforms tWL + tWH = tfCL trCL 50% 10% 10% FIGURE 2. HCT CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH tf = 6ns tr = 6ns GND tTHL tTLH 1.3V 10% INVERTING OUTPUT tPHL FIGURE 3. HC TRANSITION TIMES AND PROPAGATION DELAY TIMES, COMBINATION LOGIC trCL VCC tfCL GND 1.3V 0.3V GND tH(H) tH(L) VCC DATA INPUT 3V 2.7V CLOCK INPUT 50% tH(H) tPLH FIGURE 4.
PAGE 8
CD54HC259, CD74HC259, CD54HCT259, CD74HCT259 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE 90% 50% 10% OUTPUTS ENABLED 2.7 1.3 OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 7. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel Diameter Width (mm) W1 (mm) A0 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT259M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 19-Mar-2008 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC259M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT259M96 SOIC D 16 2500 333.2 345.9 28.
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