Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS175D
Features
• Typical Propagation Delay = 17ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
• Replaces LS180 Types
• Easily Cascadable
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
• HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
≤ 1µA at V
OL
, V
OH
Description
The ’HC280 and ’HCT280 are 9-bit odd/even parity, generator
checker devices. Both even and odd parity outputs are
available for checking or generating parity for words up to nine
bits long. Even parity is indicated (ΣE output is high) when an
even number of data inputs is high. Odd parity is indicated
(ΣO output is high) when an odd number of data inputs is
high. Parity checking for words larger than 9 bits can be
accomplished by tying the ΣE output to any input of an
additional HC/HCT280 parity checker.
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C) PACKAGE
CD54HC280F3A -55 to 125 14 Ld CERDIP
CD54HCT280F3A -55 to 125 14 Ld CERDIP
CD74HC280E -55 to 125 14 Ld PDIP
CD74HC280MT -55 to 125 14 Ld SOIC
CD74HC280M96 -55 to 125 14 Ld SOIC
CD74HCT280E -55 to 125 14 Ld PDIP
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel. The suffix T denotes a small-quantity reel
of 250.
Pinout
CD54HC280, CD54HCT280
(CERDIP)
CD74HC280
(PDIP, SOIC)
CD74HCT280
(PDIP)
TOP VIEW
Functional Diagram
I6
I7
NC
I8
ΣE
ΣO
GND
V
CC
I5
I4
I3
I2
I1
I0
1
2
3
4
5
6
7
14
13
12
11
10
9
8
8
9
10
11
13
2
1
12
5
6
∑ ODD
∑ EVEN
I0
I1
I2
I3
I5
I6
I7
I4
4
I8
GND = 7
V
CC
= 14
NC = 3
November 1997 - Revised October 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC280, CD74HC280,
CD54HCT280, CD74HCT280
High-Speed CMOS Logic
9-Bit Odd/Even Parity Generator/Checker
[
/Title
(
CD74
H
C280
,
C
D74
H
CT28
0
)
/
Sub-
j
ect
(
High
S
peed
C
MOS
L
ogic
9
-Bit
O
dd/E
v
en
P
arity