Datasheet

1
Data sheet acquired from Harris Semiconductor
SCHS198C
Features
• Maximum Frequency, Typically 60MHz
C
L
= 15pF, V
CC
= 5V, T
A
= 25
o
C
• Positive-Edge Clocking
• Overriding Reset
• Buffered Inputs and Outputs
• Fanout (Over Temperature Range)
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
• Wide Operating Temperature Range . . . -55
o
C to 125
o
C
• Balanced Propagation Delay and Transition Times
• Significant Power Reduction Compared to LSTTL
Logic ICs
• HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
Description
The ’HC4015 consists of two identical, independent, 4-stage
serial-input/parallel-output registers. Each register has
independent Clock (CP) and Reset (MR) inputs as well as a
single serial Data input. “Q” outputs are available from each
of the four stages on both registers. All register stages are D-
type, master-slave flip-flops. The logic level present at the
Data input is transferred into the first register stage and
shifted over one stage at each positive- going clock
transition. Resetting of all stages is accomplished by a high
level on the reset line.
The device can drive up to 10 low power Schottky equivalent
loads. The ’HC4015 is an enhanced version of equivalent
CMOS types.
Pinout
CD54HC4015
(CERDIP)
CD74HC4015
(PDIP, SOIC)
TOP VIEW
Ordering Information
PART NUMBER TEMP. RANGE (
o
C) PACKAGE
CD54HC4015F3A -55 to 125 16 Ld CERDIP
CD74HC4015E -55 to 125 16 Ld PDIP
CD74HC4015M -55 to 125 16 Ld SOIC
14
15
16
9
13
12
11
10
1
2
3
4
5
7
6
8
2CP
2Q
3
1Q
2
1Q
1
1Q
0
1MR
GND
1D
V
CC
2MR
2Q
0
2Q
1
2Q
2
1Q
3
1CP
2D
November 1997 - Revised May 2003
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
© 2003, Texas Instruments Incorporated
CD54HC4015, CD74HC4015
High Speed CMOS Logic
Dual 4-Stage Static Shift Register
[ /Title
(CD74
HC401
5)
/
Sub-
j
ect
(High
Speed
CMOS
Logic
Dual
4-