Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Binary counter 74HC Negative slope 35 MHz SOIC 14

Data sheet acquired from Harris Semiconductor

SCHS202C

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative Edge Clocking

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary

counters. All counter stages are master-slave ﬂip-ﬂops. The

state of the stage advances one count on the negative

transition of each input pulse; a high voltage level on the MR

line resets all counters to their zero state. All inputs and

outputs are buffered.

Pinout

CD54HC4024, CD54HCT4024

(CERDIP)

CD74HC4024

(PDIP, SOIC, TSSOP)

CD74HCT4024

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4024F3A -55 to 125 14 Ld CERDIP

CD54HCT4024F3A -55 to 125 14 Ld CERDIP

CD74HC4024E -55 to 125 14 Ld PDIP

CD74HC4024M -55 to 125 14 Ld SOIC

CD74HC4024MT -55 to 125 14 Ld SOIC

CD74HC4024M96 -55 to 125 14 Ld SOIC

CD74HC4024PW -55 to 125 14 Ld TSSOP

CD74HC4024PWR -55 to 125 14 Ld TSSOP

CD74HC4024PWT -55 to 125 14 Ld TSSOP

CD74HCT4024E -55 to 125 14 Ld PDIP

CD74HCT4024M -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

GND

’

November 1997 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4024, CD74HC4024,

CD54HCT4024, CD74HCT4024

High-Speed CMOS Logic

7-Stage Binary Ripple Counter

[

/Title

(

CD74

C402

D74

CT40

Sub-

ect

(

High

peed

MOS

Summary of content (17 pages)

PAGE 1
[ /Title (CD74 HC402 4, CD74 HCT40 24) /Subject (High Speed CMOS CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Data sheet acquired from Harris Semiconductor SCHS202C High-Speed CMOS Logic 7-Stage Binary Ripple Counter November 1997 - Revised October 2003 Features Description • Fully Static Operation The ’HC4024 and ’HCT4024 are 7-stage ripple-carry binary counters. All counter stages are master-slave flip-flops.
PAGE 2
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Functional Diagram 12 CP Q1’ 11 1 Q2 9 Q3 6 Q4 5 Q5 4 2 MR Q6 3 Q7 TRUTH TABLE CP COUNT MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs Are Low H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
PAGE 3
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . .
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CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
PAGE 5
CD54HC4024, CD74HC4024, CD54HCT4024, CD74HCT4024 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tW 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns fMAX 4.5 25 - 20 - 16 - MHz tW 4.5 20 - 25 - 30 - ns tREC 4.5 10 - 13 - 15 - ns tW 4.
PAGE 6
CD54/74HC4024, CD54/74HCT4024 Switching Specifications Input tr, tf = 6ns PARAMETER Output Transition (Continued) 25oC -40oC TO 85oC -55oC TO 125oC TEST SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tTLH, tTHL CL = 50pF 4.5 - - 15 - 19 - 22 ns Input Capacitance CIN CL =15pF - - - 10 - 10 - 10 pF Power Dissipation Capacitance (Notes 3, 4) CPD CL =15pF 5 - 30 - - - - - pF NOTES: 3. CPD is used to determine the dynamic power consumption, per package.
PAGE 7
PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 Orderable Device Status (1) Package Type Package Drawing CD74HCT4024MG4 ACTIVE SOIC D Pins Package Eco Plan (2) Qty Lead/Ball Finish MSL Peak Temp (3) no Sb/Br) 14 50 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC4024M96 Package Package Pins Type Drawing SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC4024MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC4024PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4024M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC4024MT SOIC D 14 250 367.0 367.0 38.0 CD74HC4024PWR TSSOP PW 14 2000 367.0 367.0 35.0 CD74HC4024PWT TSSOP PW 14 250 367.0 367.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.