Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter SMD 74 HC 4040 Binary counter 74HC Negative slope 35 MHz SOIC 16

Data sheet acquired from Harris Semiconductor

SCHS203D

Features

• Fully Static Operation

• Buffered Inputs

• Common Reset

• Negative Edge Pulsing

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4040 and ’HCT4040 are 14-stage ripple-carry

binary counters. All counter stages are master-slave ﬂip-

ﬂops. The state of the stage advances one count on the

negative clock transition of each input pulse; a high voltage

level on the MR line resets all counters to their zero state. All

inputs and outputs are buffered.

Pinout

CD54HC4040, CD54HCT4040

(CERDIP)

CD74HC4040

(PDIP, SOIC, SOP)

CD74HCT4040

(PDIP, SOIC)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4040F3A -55 to 125 16 Ld CERDIP

CD54HCT4040F3A -55 to 125 16 Ld CERDIP

CD74HC4040E -55 to 125 16 Ld PDIP

CD74HC4040M -55 to 125 16 Ld SOIC

CD74HC4040MT -55 to 125 16 Ld SOIC

CD74HC4040M96 -55 to 125 16 Ld SOIC

CD74HC4040NSR -55 to 125 16 Ld SOP

CD74HCT4040E -55 to 125 16 Ld PDIP

CD74HCT4040M -55 to 125 16 Ld SOIC

CD74HCT4040MT -55 to 125 16 Ld SOIC

CD74HCT4040M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

GND

‘

February 1998 - Revised October 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4040, CD74HC4040,

CD54HCT4040, CD74HCT4040

High-Speed CMOS Logic

12-Stage Binary Counter

[

/Title

(

CD74H

4040,

D74HC

4040)

Subject

(

High

peed

MOS

ogic

2-Stage

inary

Summary of content (14 pages)

PAGE 1
[ /Title (CD74H C4040, CD74HC T4040) /Subject (High Speed CMOS Logic 12-Stage Binary CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Data sheet acquired from Harris Semiconductor SCHS203D High-Speed CMOS Logic 12-Stage Binary Counter February 1998 - Revised October 2003 Features Description • Fully Static Operation The ’HC4040 and ’HCT4040 are 14-stage ripple-carry binary counters. All counter stages are master-slave flipflops.
PAGE 2
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Functional Diagram VCC 16 10 9 INPUT PULSES 7 6 5 3 12-STAGE RIPPLE COUNTER 2 4 13 12 14 15 1 11 MASTER RESET Q1’ Q2 Q3 Q4 Q5 Q6 BUFFERED OUTPUTS Q7 Q8 Q9 Q10 Q11 Q12 8 GND TRUTH TABLE CP COUNT MR OUTPUT STATE ↑ L No Change ↓ L Advance to Next State X H All Outputs Are Low H = High Voltage Level, L = Low Voltage Level, X = Don’t Care, ↑ = Transition from Low to High Level, ↓ = Transition from High to Low.
PAGE 3
MR CP 11 10 Q1’ R R 9 CP Q 2 CP Q CP Q I Q’ CP Q Q2 7 R CP Q 3 CP Q Q3 6 R CP Q 4 CP Q Q4 5 R CP Q 5 CP Q Q5 3 R CP Q 6 CP Q Q6 2 R CP Q 7 CP Q Q7 4 R CP Q 8 CP Q Q8 13 R CP Q 9 CP Q Q9 12 R CP Q 10 CP Q Q10 14 R CP Q 11 CP Q Q11 15 R CP Q 12 CP Q Q12 1 CD54/74HC4040, CD54/74HCT4040 Logic Diagram 3
PAGE 4
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . .
PAGE 5
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 DC Electrical Specifications (Continued) TEST CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS High Level Input Voltage VIH - - 4.5 to 5.5 2 - - 2 - 2 - V Low Level Input Voltage VIL - - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V High Level Output Voltage CMOS Loads VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.7 - V 0.
PAGE 6
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Prerequisite for Switching Specifications (Continued) 25oC PARAMETER Reset Removal Time Reset Pulse Width -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN MAX MIN MAX MIN MAX UNITS tREM 2 50 - 65 - 75 - ns 4.5 10 - 13 - 15 - ns 6 9 - 11 - 13 - ns 2 80 - 100 - 120 - ns 4.5 16 - 20 - 24 - ns 6 14 - 17 - 20 - ns fMAX 4.5 25 - 20 - 16 - MHz tW 4.5 20 - 25 - 30 - ns tREM 4.
PAGE 7
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Switching Specifications Input tr, tf = 6ns PARAMETER SYMBOL Qn to Qn + 1 (Continued) TEST CONDITIONS tPLH, tPHL CL = 50pF tPLH, tPHL CL = 50pF MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 - - 15 - 19 - 22 ns 5 - 4 - - - - - ns 4.5 - - 40 - 50 - 60 ns 5 - 17 - - - - - ns 4.
PAGE 8
CD54HC4040, CD74HC4040, CD54HCT4040, CD74HCT4040 Test Circuits and Waveforms trCL tfCL trCL CLOCK INPUT (Continued) VCC 90% GND tH(H) GND tH(H) VCC DATA INPUT 50% tH(L) 3V 1.3V 1.3V 1.3V GND tSU(H) tSU(H) tSU(L) tTLH 90% OUTPUT tTHL 90% 50% 10% tTLH 90% 1.3V OUTPUT tREM 3V SET, RESET OR PRESET GND tTHL 1.3V 10% FIGURE 5. HC SETUP TIMES, HOLD TIMES, REMOVAL TIME, AND PROPAGATION DELAY TIMES FOR EDGE TRIGGERED SEQUENTIAL LOGIC CIRCUITS tPHL 1.
PAGE 9
PACKAGE OPTION ADDENDUM www.ti.
PAGE 10
PACKAGE OPTION ADDENDUM www.ti.com 24-Sep-2015 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant CD74HC4040M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HCT4040M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
PAGE 13
PACKAGE MATERIALS INFORMATION www.ti.com 29-Jul-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4040M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HCT4040M96 SOIC D 16 2500 333.2 345.9 28.
PAGE 14
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.