Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Counter Division by N 74HC Positive slope 32 MHz SOIC 24

Data sheet acquired from Harris Semiconductor

SCHS206B

Features

• Synchronous Programmable ÷N Counter N = 3 to 9999

or 15999

• Presettable Down-Counter

• Fully Static Operation

• Mode-Select Control of Initial Decade Counting

Function (÷10, 8, 5, 4, 2)

• Master Preset Initialization

• Latchable ÷N Output

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

Applications

• Communications Digital Frequency Synthesizers;

VHF, UHF, FM, AM, etc.

• Fixed or Programmable Frequency Division

• “Time Out” Timer for Consumer-Application Industrial

Controls

Description

The ’HC4059 are high-speed silicon-gate devices that are

pin-compatible with the CD4059A devices of the CD4000B

series. These devices are divide-by-N down-counters that

can be programmed to divide an input frequency by any

number “N” from 3 to 15,999. The output signal is a pulse

one clock cycle wide occurring at a rate equal to the input

frequency divide by N. The down-counter is preset by means

of 16 jam inputs.

The three Mode-Select Inputs K

and K

determine the

modulus (“divide-by” number) of the first and last counting

sections in accordance with the truth table. Every time the first

(fastest) counting section goes through one cycle, it reduces by

1 the number that has been preset (jammed) into the three

decades of the intermediate counting section an the last

counting section, which consists of flip-flops that are not

needed for opening the first counting section. For example, in

the ÷2 mode, only one flip-flop is needed in the first counting

section. Therefore the last counting section has three flip-flops

that can be preset to a maximum count of seven with a place

value of thousands. If ÷10 is desired for the first section, K

set “high”, K

“high” and K

“low”. Jam inputs J1, J2, J3, and J4

are used to preset the first counting section and there is no last

counting section. The intermediate counting section consists of

three cascaded BCD decade (÷10) counters presettable by

means of Jam Inputs J5 through J16.

The Mode-Select Inputs permit frequency-synthesizer

channel separations of 10, 12.5, 20, 25 or 50 parts. These

inputs set the maximum value of N at 9999 (when the ﬁrst

counting section divides by 5 or 10) or 15,999 (when the ﬁrst

counting section divides by 8, 4, or 2).

The three decades of the intermediate counter can be preset

to a binary 15 instead of a binary 9, while their place values

are still 1, 10, and 100, multiplied by the number of the ÷N

mode. For example, in the ÷8 mode, the number from which

counting down begins can be preset to:

3rd Decade 1500

2nd Decade 150

1st Decade 15

Last Counting Section 1000

The total of these numbers (2665) times 8 equals 12,320.

The ﬁrst counting section can be preset to 7. Therefore,

21,327 is the maximum possible count in the ÷8 mode.

The highest count of the various modes is shown in the

Extended Counter Range column. Control inputs K

and K

can be used to initiate and lock the counter in the “master

preset” state. In this condition the flip-flops in the counter are

preset in accordance with the jam inputs and the counter

remains in that state as long as K

and K

both remain low. The

counter begins to count down from the preset state when a

counting mode other than the master preset mode is selected.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4059F3A -55 to 125 24 Ld CERDIP

CD74HC4059E -55 to 125 24 Ld PDIP

CD74HC4059M96 -55 to 125 24 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

February 1998 - Revised May 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4059, CD74HC4059

High-Speed CMOS Logic

CMOS Programmable Divide-by-N Counter

[ /Title

(CD74

HC4059

)

/Sub-

ject

(High-

Speed

CMOS

Logic

CMOS

Pro-

Summary of content (13 pages)

PAGE 1
[ /Title (CD74 HC4059 ) /Subject (HighSpeed CMOS Logic CMOS Pro- CD54HC4059, CD74HC4059 Data sheet acquired from Harris Semiconductor SCHS206B High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter February 1998 - Revised May 2003 Features Description • Synchronous Programmable ÷N Counter N = 3 to 9999 or 15999 The ’HC4059 are high-speed silicon-gate devices that are pin-compatible with the CD4059A devices of the CD4000B series.
PAGE 2
CD54HC4059, CD74HC4059 Pinout The counter should always be put in the master preset mode before the ÷5 mode is selected. Whenever the master preset mode is used, control signals Kb = “low” and Kc = “low” must be applied for at least 3 full clock pulses.
PAGE 3
CD54HC4059, CD74HC4059 How to Preset the HC/HCT4059 to Desired ÷N The value N is determined as follows: N Preset Value = Mode (EQ. 1) N = (MODE†) (1000 x Decade 5 Preset + 100 x Decade 4 Preset + 10 x Decade 3 Preset + 1 x Decade 2 Preset) + Decade 1 Preset Example: N = 8479, Mode = 5 † MODE = First counting section divider (10, 8, 5, 4 or 2) To calculate preset values for any N count, divide the N count by the Mode.
PAGE 4
CD54HC4059, CD74HC4059 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .
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CD54HC4059, CD74HC4059 Prerequisite for Switching Specifications 25oC PARAMETER Pulse Width CP Setup Time Kb, Kc to CP CP Frequency -40oC TO 85oC -55oC TO 125oC SYMBOL VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS tW 2 90 - - 115 - - 135 - - ns 4.5 18 - - 23 - - 27 - - ns 6 15 - - 20 - - 23 - - ns 2 75 - - 95 - - 110 - - ns 4.5 15 - - 19 - - 22 - - ns 6 13 - - 16 - - 19 - - ns 2 5 - - 4 - - 4 - - MHz 4.
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CD54HC4059, CD74HC4059 Test Circuits and Waveforms tr = 6ns tfCL trCL CLOCK 90% 10% I tWL + tWH = fCL tf = 6ns VCC 50% 10% tWL 50% VCC 90% 50% 10% INPUT GND 50% tTHL GND tTLH 90% 50% 10% tWH INVERTING OUTPUT NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. tPHL FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND PULSE WIDTH FIGURE 3.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 8
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 9
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC4059M96 Package Package Pins Type Drawing SOIC DW 24 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.7 2.7 12.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4059M96 SOIC DW 24 2000 367.0 367.0 45.
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MECHANICAL DATA MPDI006B – SEPTEMBER 2001 – REVISED APRIL 2002 N (R–PDIP–T24) PLASTIC DUAL–IN–LINE 1.222 (31,04) MAX 24 13 0.360 (9,14) MAX 1 12 0.070 (1,78) MAX 0.200 (5,08) MAX 0.425 (10,80) MAX 0.020 (0,51) MIN Seating Plane 0.125 (3,18) MIN 0.100 (2,54) 0’–15’ 0.021 (0,53) 0.015 (0,38) 0.010 (0,25) 0.010 (0,25) NOM 4040051–3/D 09/01 NOTES: A. All linear dimensions are in inches (millimeters). B. This drawing is subject to change without notice. C.
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