Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Gate OR gate 74HC PDIP 14

Data sheet acquired from Harris Semiconductor

SCHS210G

Features

• Buffered Inputs

• Typical Propagation Delay: 8ns at V

= 5V,

= 15pF, T

= 25

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate

CMOS technology to achieve operating speeds similar to

LSTTL gates with the low power consumption of standard

CMOS integrated circuits. All devices have the ability to drive

10 LSTTL loads. The HCT logic family is functionally pin

compatible with the standard LS logic family.

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4075F3A -55 to 125 14 Ld CERDIP

CD54HC4075FK -55 to 125 20 LCCC

CD54HCT4075F3A -55 to 125 14 Ld CERDIP

CD74HC4075E -55 to 125 14 Ld PDIP

CD74HC4075M -55 to 125 14 Ld SOIC

CD74HC4075MT -55 to 125 14 Ld SOIC

CD74HC4075M96 -55 to 125 14 Ld SOIC

CD74HC4075NSR -55 to 125 14 Ld SOP

CD74HC4075PW -55 to 125 14 Ld TSSOP

CD74HC4075PWR -55 to 125 14 Ld TSSOP

CD74HC4075PWT -55 to 125 14 Ld TSSOP

CD74HCT4075E -55 to 125 14 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

August 1997 - Revised June 2006

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4075, CD74HC4075,

CD54HCT4075, CD74HCT4075

High-Speed CMOS Logic

Triple 3-Input OR Gate

[ /Title

(CD74H

C4075,

CD74H

CT4075)

/Subject

(High

Speed

CMOS

Logic

Triple 3-

Input

Summary of content (20 pages)

PAGE 1
[ /Title (CD74H C4075, CD74H CT4075) /Subject (High Speed CMOS Logic Triple 3Input CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Data sheet acquired from Harris Semiconductor SCHS210G High-Speed CMOS Logic Triple 3-Input OR Gate August 1997 - Revised June 2006 Features Description • Buffered Inputs The ’HC4075 and ’HCT4075 logic gates utilize silicon-gate CMOS technology to achieve operating speeds similar to LSTTL gates with the low power consumption of standard CMOS integrated circuits.
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Pinout CD54HC4075, CD54HCT4075 (CERDIP) CD74HC4075 (PDIP, SOIC, SOP, TSSOP) CD74HCT4075 (PDIP) TOP VIEW 2A 1 14 VCC 2B 2 13 3C 1A 3 12 3B 1B 4 11 3A 1C 5 10 3Y 1Y 6 9 2Y GND 7 8 2C 2B 2A NC VCC 3C SN54HC4075 (FK) (TOP VIEW) 3 2 1 20 19 5 17 NC 1B 6 16 3A NC 7 15 NC 1C 8 14 3Y 9 10 2 11 12 13 2Y NC 2C 3B NC 18 GND 4 1Y 1A
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Functional Diagram 1A 1B 1C 2A 2B 2C 3A 3 6 4 1 9 2 2Y 8 11 10 12 3Y GND = 7 VCC = 14 3B 3C 1Y 5 13 TRUTH TABLE INPUTS OUTPUT nA nB nC nY L L L L H X X H X H X H X X H H H = High Voltage Level, L = Low Voltage Level, X = Irrelevant Logic Diagram nA nY nB nC 3
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . .
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CD54HC4075, CD74HC4075, CD54HCT4075, CD74HCT4075 DC Electrical Specifications (Continued) TEST CONDITIONS SYMBOL VI (V) IO (mA) High Level Input Voltage VIH - - Low Level Input Voltage VIL - High Level Output Voltage CMOS Loads VOH VIH or VIL PARAMETER 25oC VCC (V) -40oC TO 85oC -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V -0.02 4.5 4.4 - - 4.4 - 4.4 - V -4 4.5 3.98 - - 3.84 - 3.
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Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS Power Dissipation Capacitance (Notes 3, 4) CPD - 5 - 26 - - - - - pF Propagation Delay, Input to Output (Figure 2) tPLH, tPHL CL = 50pF 4.5 - - 24 - 30 - 36 ns CL = 15pF 5 - 9 - - - - - ns Transition Times (Figure 2) tTLH, tTHL CL = 50pF 4.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 25-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
PAGE 10
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC4075M96 SOIC D 14 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 6.5 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 9.0 2.1 8.0 16.0 Q1 CD74HC4075MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1 CD74HC4075NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4075M96 SOIC D 14 2500 367.0 367.0 38.0 CD74HC4075MT SOIC D 14 250 367.0 367.0 38.0 CD74HC4075NSR SO NS 14 2000 367.0 367.0 38.0 CD74HC4075PWR TSSOP PW 14 2000 367.0 367.0 35.0 CD74HC4075PWT TSSOP PW 14 250 367.0 367.0 35.
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