Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsInterface ICsInterface IC - multiplexers, demultiplexers PDIP 20

Data sheet acquired from Harris Semiconductor

SCHS213C

Features

• Wide Analog Input Voltage Range . . . . . . . . . ±5V (Max)

• Low “On” Resistance

-V

- V

= 4.5V. . . . . . . . . . . . . . . . . . . . . .70Ω (Typ)

-V

- V

= 9V . . . . . . . . . . . . . . . . . . . . . . .40Ω (Typ)

• Low Crosstalk Between Switches

• Fast Switching and Propagation Speeds

• “Break-Before-Make” Switching

• Wide Operating Temperature Range . . . -55

C to 125

• HC Types

- 2V to 6V Operation, Control; 0V to 10V Switch

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation, Control; 0V to 10V Switch

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Description

The ’HC4351, CD74HCT4351, and CD74HC4352 are

digitally controlled analog switches which utilize silicon-gate

CMOS technology to achieve operating speeds similar to

LSTTL with the low power consumption of standard CMOS

integrated circuits.

These analog multiplexers/demultiplexers are, in essence,

the HC/HCT4015 and HC4052 preceded by address latches

that are controlled by an active low Latch Enable input (

LE).

Two Enable inputs, one active low (

E1), and the other active

high (E2) are provided allowing enabling with either input

voltage level.

Pinouts

CD54HC4351

(CERDIP)

CD74HC4351

(PDIP, SOIC)

CD74HCT4351

(PDIP)

TOP VIEW

CD74HC4352

(PDIP)

TOP VIEW

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4351F3A -55 to 125 20 Ld CERDIP

CD74HC4351E -55 to 125 20 Ld PDIP

CD74HC4351M -55 to 125 20 Ld SOIC

CD74HC4351M96 -55 to 125 20 Ld SOIC

CD74HCT4351E -55 to 125 20 Ld PDIP

CD74HC4352E -55 to 125 20 Ld PDIP

NOTE: When ordering, use the entire part number. The sufﬁx 96

denotes tape and reel.

A COMMON

GND

B COMMON

GND

A COMMON

September 1998 - Revised July 2003

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4351, CD74HC4351,

CD74HCT4351, CD74HC4352

High-Speed CMOS Logic

Analog Multiplexers/Demultiplexers with Latch

[ /Title

(CD74

HC435

CD74

HCT43

51,

CD74

HC435

Sub-

ect

(High

Speed

CMOS

Logic

Ana-

log

Multi-

plex-

ers/De

multi-

plex-

ers

with

Latch)

Autho

r ()

Key-

words

(High

Speed

CMOS

Logic

Summary of content (24 pages)

PAGE 1
[ /Title (CD74 HC435 1, CD74 HCT43 51, CD74 HC435 2) /Subject (High Speed CMOS Logic Analog Multiplexers/De multiplexers with Latch) /Autho r () /Keywords (High Speed CMOS Logic CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Data sheet acquired from Harris Semiconductor SCHS213C September 1998 - Revised July 2003 High-Speed CMOS Logic Analog Multiplexers/Demultiplexers with Latch Features CMOS technology to achieve operating speeds similar to LSTTL with the low power consumption of standard CMOS integ
PAGE 2
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Functional Diagram ’HC4351, CD74HCT4351 CHANNEL IN/OUT VCC 20 A7 A6 A5 A4 A3 A2 A1 A0 5 2 6 1 16 19 18 17 TG S0 15 TG S1 13 S2 12 TG LATCHES TG BINARY TO 1 OF 8 DECODER WITH ENABLE LOGIC LEVEL CONVERSION LE 11 4 A COMMON OUT/IN TG TG E1 TG 7 TG E2 8 10 GND 9 VEE TRUTH TABLE ’HC4351, CD74HCT4351 INPUT STATES E1 E2 S2 S1 S0 (NOTE 1) “ON” SWITCHES LE = H L H L L L A0 H L L H A1 L H L H L A2 L H L
PAGE 3
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Functional Diagram CD74HC4352 A CHANNELS IN/OUT VCC A3 A2 A1 A0 15 19 18 16 20 TG S0 13 S0 S0 LATCHES S1 12 LE TG S1 TG S1 BINARY TO 1 OF 4 DECODER WITH ENABLE LOGIC LEVEL CONVERSION 11 TG 17 A COMMON OUT/IN TG 4 B COMMON OUT/IN TG E1 7 E2 8 TG TG 10 9 GND 5 2 6 1 B0 B1 B2 B3 B CHANNELS IN/OUT VEE TRUTH TABLE CD74HC4352 An (Bn) IN/OUT INPUT STATES E1 E2 S1 S0 FROM SELECT LOGIC (NOTE 2) “ON” SWITCHES LE =
PAGE 4
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Supply Voltage, VCC - VEE . . . . . . . . . . . . . . . . . . -0.5V to 10.5V DC Supply Voltage, VEE . . . . . . . . . . . . . . . . . . . . . . . . 0.5V to -7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC 0.5V. . . . . . . . . . . . . . . . . . . . . . . .±20mA DC Switch Diode Current, IOK For VI < VEE -0.
PAGE 5
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 DC Electrical Specifications PARAMETER -40oC TO 85oC 25oC TEST CONDITIONS -55oC TO 125oC SYMBOL VI (V) VIS (V) VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS VIH - - - 2 1.5 - - 1.5 - 1.5 - V 4.5 3.15 - - 3.15 - 3.15 - V 6 4.2 - - 4.2 - 4.2 - V 2 - - 0.5 - 0.5 - 0.5 V 4.5 - - 1.35 - 1.35 - 1.35 V 6 - - 1.8 - 1.8 - 1.8 V 0 4.
PAGE 6
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 DC Electrical Specifications (Continued) SYMBOL VI (V) VIS (V) VEE (V) VCC (V) High Level Input Voltage VIH - - - Low Level Input Voltage VIL - - “ON” Resistance IO = 1mA Figure 9 RON VIH or VIL VCC or VEE PARAMETER -40oC TO 85oC 25oC TEST CONDITIONS -55oC TO 125oC MIN TYP MAX MIN MAX MIN MAX UNITS 4.5 to 5.5 2 - - 2 - 2 - V - 4.5 to 5.5 - - 0.8 - 0.8 - 0.8 V 0 4.5 - 70 160 - 200 - 240 Ω -4.5 4.
PAGE 7
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Switching Specifications Input tr, tf = 6ns -40oC TO 85oC 25oC PARAMETER -55oC TO 125oC SYMBOL TEST CONDITIONS VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPLH, tPHL CL = 50pF 0 2 - - 35 - 45 - 55 ns 0 4.5 - - 7 - 9 - 11 ns 0 6 - - 6 - 8 - 9 ns -4.5 4.5 - - 5 - 7 - 8 ns 0 2 - - 300 - 375 - 450 ns 0 4.5 - - 60 - 75 - 90 ns 0 6 - - 51 - 64 - 77 ns -4.5 4.
PAGE 8
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC PARAMETER Maximum Switch Turn “OFF” Delay 4351 E2 to VOS Maximum Switch Turn “OFF” Delay 4351 LE to VOS Maximum Switch Turn “OFF” Delay 4351 Sn to VOS Maximum Switch Turn “OFF” Delay 4352 E1, E2, LE to VOS Setup Time 4351 Sn to LE Hold Time 4351 and 4352 Sn to LE Pulse Width 4351 and 4352 LE Input (Control) Capacitance Power Dissipation Capacitance (Notes 6, 7) 4351 -55oC TO 1
PAGE 9
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Switching Specifications Input tr, tf = 6ns (Continued) -40oC TO 85oC 25oC -55oC TO 125oC PARAMETER SYMBOL TEST CONDITIONS VEE (V) VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS Power Dissipation Capacitance (Notes 6, 7) 4352 CPD - - 5 - 74 - - - - - pF tPLH, tPHL CL = 50pF 0 4.5 - - 7 - 9 - 11 ns -4.5 4.5 - - 5 - 7 - 8 ns 0 4.5 - - 75 - 94 - 113 ns -4.5 4.
PAGE 10
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Analog Channel Specifications PARAMETER Switch Input Capacitance Common Capacitance Minimum Switch Frequency Response at -3dB (Figure 6, 8) TA = 25oC SYMBOL TEST CONDITIONS TYPE VEE (V) VCC (V) HC/HCT UNITS CI All - - 5 pF CCOM 4351 - - 25 pF 4352 - - 12 pF 4351 - - 145 MHz 4352 -2.25 2.
PAGE 11
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Typical Performance Curves 0 0 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 12 TO 3 -2 -4 -40 dB dB VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 12 TO 3 -6 VCC = 2.25V GND = -2.25V VEE = -2.25V RL = 50Ω PIN 12 TO 3 -20 -60 -8 VCC = 4.5V GND = -4.5V VEE = -4.5V RL = 50Ω PIN 12 TO 3 -80 -10 10K 100K 1M 10M FREQUENCY, f (Hz) -100 10K 100M FIGURE 5. CHANNEL ON BANDWIDTH (’HC4351, CD74HCT4351) 1M 10M FREQUENCY, f (Hz) 100M FIGURE 6.
PAGE 12
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 “ON” RESISTANCE, RON (Ω) Typical Performance Curves (Continued) 130 120 110 100 90 80 70 60 50 40 30 20 10 VCC - VEE = 4.5V VCC - VEE = 6V VCC - VEE = 9V 0 1 0 2 3 4 5 6 7 8 9 INPUT SIGNAL VOLTAGE, VIS (V) FIGURE 9. TYPICAL ON RESISTANCE vs INPUT SIGNAL VOLTAGE Analog Test Circuits VIS 0.1µF VCC VCC SWITCH ON VIS R VOS1 R R C VOS2 SWITCH OFF R VCC/2 VCC/2 C dB METER VCC/2 fIS = 1MHz SINEWAVE R = 50Ω C = 10pF FIGURE 10.
PAGE 13
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Analog Test Circuits (Continued) E VCC 600Ω VCC/2 SWITCH ALTERNATING ON AND OFF tr, tf ≤ 6ns fCONT = 1MHz 50% DUTY CYCLE VCC VP-P VOS 0.1µF 600Ω 50pF VCC/2 SCOPE FIGURE 13. CONTROL-TO-SWITCH FEEDTHROUGH NOISE TEST CIRCUIT fIS ≥ 1MHz SINEWAVE R = 50Ω C = 10pF VOS SWITCH OFF VIS VOS VC = VIL R R VCC/2 VCC/2 C dB METER FIGURE 14.
PAGE 14
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Test Circuits and Waveforms tWL + tWH = tfCL trCL tWL + tWH = trCL = 6ns tfCL = 6ns 50% 10% 10% 2.7V CLOCK 50% 50% 1.3V 0.3V 0.3V GND 1.3V 1.3V GND tWH tWL tWH tWL I fCL 3V VCC 90% CLOCK I fCL NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table. For fMAX, input duty cycle = 50%. NOTE: Outputs should be switching from 10% VCC to 90% VCC in accordance with device truth table.
PAGE 15
CD54HC4351, CD74HC4351, CD74HCT4351, CD74HC4352 Test Circuits and Waveforms 6ns (Continued) 6ns OUTPUT DISABLE tr VCC 90% 50% 10% OUTPUTS ENABLED OUTPUT HIGH TO OFF 50% OUTPUTS DISABLED FIGURE 21. HC THREE-STATE PROPAGATION DELAY WAVEFORM OTHER INPUTS TIED HIGH OR LOW OUTPUT DISABLE IC WITH THREESTATE OUTPUT GND 1.3V tPZH 90% OUTPUTS ENABLED OUTPUTS ENABLED 0.3 10% tPHZ tPZH 90% 3V tPZL tPLZ OUTPUT LOW TO OFF 50% OUTPUT HIGH TO OFF 6ns GND 10% tPHZ tf 2.7 1.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com 15-Oct-2009 information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC4351M96 Package Package Pins Type Drawing SOIC DW 20 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 24.4 Pack Materials-Page 1 10.8 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 2.7 12.0 24.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4351M96 SOIC DW 20 2000 367.0 367.0 45.
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