Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Multivibrator Monostable 21 ns SOIC 16 N

Data sheet acquired from Harris Semiconductor

SCHS123E

Features

• Retriggerable/Resettable Capability

• Trigger and Reset Propagation Delays Independent of

, C

• Triggering from the Leading or Trailing Edge

• Q and

Q Buffered Outputs Available

• Separate Resets

• Wide Range of Output Pulse Widths

• Schmitt Trigger Input on A and

B Inputs

• Retrigger Time is Independent of C

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating Temperature Range . . . -55

C to 125

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: N

= 30%, N

= 30% of V

at V

= 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

= 0.8V (Max), V

= 2V (Min)

- CMOS Input Compatibility, I

≤ 1µA at V

, V

Pinout

CD54HC4538, CD54HCT4538

(CERDIP)

CD74HC4538

(PDIP, SOIC, SOP, TSSOP)

CD74HCT4538

(PDIP, SOIC)

TOP VIEW

Description

The ’HC4538 and ’HCT4538 are dual

retriggerable/resettable monostable precision multivibrators

for ﬁxed voltage timing applications. An external resistor

) and an external capacitor (C

) control the timing and

the accuracy for the circuit. Adjustment of R

and C

provides a wide range of output pulse widths from the Q and

Q terminals. The propagation delay from trigger input-to-

output transition and the propagation delay from reset input-

to-output transition are independent of R

and C

Leading-edge triggering (A) and trailing edge triggering (

inputs are provided for triggering from either edge of the

input pulse. An unused “A” input should be tied to GND and

an unused

B should be tied to V

. On power up the IC is

reset. Unused resets and sections must be terminated. In

normal operation the circuit retriggers on the application of

each new trigger pulse. To operate in the non-triggerable

mode

Q is connected to B when leading edge triggering (A)

is used or Q is connected to A when trailing edge triggering

(

B) is used. The period (τ) can be calculated from τ = (0.7)

, C

; R

MIN

is 5kΩ. C

MIN

is 0pF.

GND

Ordering Information

PART NUMBER

TEMP. RANGE

(

C) PACKAGE

CD54HC4538F3A -55 to 125 16 Ld CERDIP

CD54HCT4538F3A -55 to 125 16 Ld CERDIP

CD74HC4538E -55 to 125 16 Ld PDIP

CD74HC4538M -55 to 125 16 Ld SOIC

CD74HC4538MT -55 to 125 16 Ld SOIC

CD74HC4538M96 -55 to 125 16 Ld SOIC

CD74HC4538NSR -55 to 125 16 Ld SOP

CD74HC4538PW -55 to 125 16 Ld TSSOP

CD74HC4538PWR -55 to 125 16 Ld TSSOP

CD74HC4538PWT -55 to 125 16 Ld TSSOP

CD74HCT4538E -55 to 125 16 Ld PDIP

CD74HCT4538M -55 to 125 16 Ld SOIC

CD74HCT4538MT -55 to 125 16 Ld SOIC

CD74HCT4538M96 -55 to 125 16 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54HC4538, CD74HC4538,

CD54HCT4538, CD74HCT4538

High-Speed CMOS Logic Dual Retriggerable

Precision Monostable Multivibrator

[

/Title

(

CD54

C453

D74

C453

D74

CT45

Sub-

ect

(

High

peed

MOS

ogic

June 1998 - Revised October 2003

Summary of content (24 pages)

PAGE 1
[ /Title (CD54 HC453 8, CD74 HC453 8, CD74 HCT45 38) /Subject (High Speed CMOS Logic CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Data sheet acquired from Harris Semiconductor SCHS123E June 1998 - Revised October 2003 High-Speed CMOS Logic Dual Retriggerable Precision Monostable Multivibrator Features Description • Retriggerable/Resettable Capability The ’HC4538 and ’HCT4538 are dual retriggerable/resettable monostable precision multivibrators for fixed voltage timing applications.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Functional Diagram 1Cx 1Rx VCC 1 2 1Cx 1RxCx 6 4 1A 1Q MONO 1 5 7 1B 1Q 3 1R 2R 13 10 12 2Q 2A MONO 2 11 9 2B 2Q 2Cx 2RxCx 15 GND = 8 VCC = 16 14 VCC 2Cx 2Rx TRUTH TABLE R2 INPUTS OUTPUTS R A B Q Q L X X L H CL R1 p n D X H X L H X X L L H Q CL CL CL Q H L ↓ p n H ↑ H CL H = High Level, L = Low Level, ↑ = Transition from Low to High, ↓ = Transition from High to Low, One High Level Pulse, One Low
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 16 VCC VCC VCC VCC RX 2(14) CX COMP II + R1 6(10) Q - 1(15) R2 VCC VCC 8 7(9) Q HIGH Z 3(13) R VCC 4(12) D R1 A CL 5(11) R2 Q FF CL Q B FIGURE 2.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Absolute Maximum Ratings Thermal Information DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V DC Input Diode Current, IIK For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA DC Output Diode Current, IOK For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA DC Output Source or Sink Current per Output Pin, IO For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . .
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 DC Electrical Specifications (Continued) TEST CONDITIONS PARAMETER Low Level Output Voltage CMOS Loads 25oC -40oC TO 85oC -55oC TO 125oC SYMBOL VI (V) IO (mA) VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V 0.02 4.5 - - 0.1 - 0.1 - 0.1 V 0.02 6 - - 0.1 - 0.1 - 0.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 HCT Input Loading Table INPUT UNIT LOADS All 0.5 NOTE: Unit Load is ∆ICC limit specified in DC Electrical Table, e.g. 360µA max at 25oC. Prerequisite for Switching Specifications 25oC PARAMETER SYMBOL -40oC TO 85oC -55oC TO 125oC VCC (V) MIN TYP MAX MIN TYP MAX MIN TYP MAX UNITS 2 80 - - 100 - - 120 - - ns 4.5 16 - - 20 - - 24 - - ns 6 14 - - 17 - - 20 - - ns 2 80 - - 100 - - 120 - - ns 4.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0 -40oC TO 85oC 25oC PARAMETER SYMBOL TEST CONDITIONS tPLH CL = 50pF -55oC TO 125oC VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS 2 - - 250 - 315 - 375 ns 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns CL = 50pF 6 - - 43 - 54 - 64 ns CL = 50pF 2 - - 250 - 315 - 375 ns 4.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Switching Specifications CL = 50pF, Input tr, tf = 6ns, RX = 10KΩ, CX = 0 (Continued) -40oC TO 85oC 25oC PARAMETER R to Q R to Q -55oC TO 125oC SYMBOL TEST CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS tPHL CL = 50pF 4.5 - - 40 - 50 - 60 ns CL = 15pF 5 - 17 - - - - - ns CL = 50pF 4.5 - - 50 - 63 - 75 ns CL = 15pF 5 - 21 - - - - - ns tPLH Output Transition Time tTLH, tTHL CL = 50pF 4.
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CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Typical Performance Curves HC4538 - TA11646C TA = 25oC 0.70 HCT4538 - TA13646C TA = 25oC 0.70 K FACTOR K FACTOR 10kΩ, 10nF 0.69 10kΩ, 100nF 100kΩ, 100nF 0.68 0.69 10kΩ, 10nF 10kΩ, 100nF 100kΩ, 100nF 0.68 100kΩ, 10nF 100kΩ, 10nF 0.67 0.67 2 3 4 4.5 5 5.5 6 2 VCC, DC SUPPLY VOLTAGE (V) trr, TYP MIN RETRIGGER TIME (ns) K FACTOR 1.1 1.0 0.9 0.8 2kΩ 0.7 10kΩ 100kΩ 102 103 104 5 5.5 104 1.2 10 4.5 6 FIGURE 9.
PAGE 10
CD54HC4538, CD74HC4538, CD54HCT4538, CD74HCT4538 Power-Down Mode During a rapid power-down condition, as would occur with a power-supply short circuit with a poorly filtered power supply, the energy stored in CX could discharge into Pin 2 or 14. To aviod possible device damage in this mode, when CX is ≥ 0.5µF, a protection diode with a 1 ampere or higher rating (1N5395 or equivalent) and a separate ground return for CX should be provided as shown in Figure 12.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device CD74HC4538M96 Package Package Pins Type Drawing SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC4538NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1 CD74HC4538PWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC4538M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC4538NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC4538PWR TSSOP PW 16 2000 367.0 367.0 35.0 CD74HC4538PWT TSSOP PW 16 250 367.0 367.0 35.0 CD74HCT4538M96 SOIC D 16 2500 333.2 345.9 28.
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