Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Shift register Shift register Three-state SOIC 16 N

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  

   

SCHS353 − JANUARY 2004

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

D 8-Bit Serial-In, Parallel-Out Shift

D Wide Operating Voltage Range of 2 V to 6 V

D High-Current 3-State Outputs Can Drive Up

To 15 LSTTL Loads

D Low Power Consumption, 80-µA Max I

D Typical t

= 14 ns

D ±6-mA Output Drive at 5 V

D Low Input Current of 1 µA Max

D Shift Register Has Direct Clear

description/ordering information

The CD74HC595 device contains an 8-bit serial-in, parallel-out shift register that feeds an 8-bit D-type storage

storage registers. The shift register has a direct overriding clear (SRCLR

) input, serial (SER) input, and serial

output for cascading. When the output-enable (OE

) input is high, the outputs are in the high-impedance state.

Both the shift register clock (SRCLK) and storage register clock (RCLK) are positive-edge triggered. If both

clocks are connected together, the shift register always is one clock pulse ahead of the storage register.

ORDERING INFORMATION

PACKAGE

†

ORDERABLE

PART NUMBER

TOP-SIDE

MARKING

PDIP − E Tube of 25 CD74HC595E CD74HC595E

SOIC − DW

Tube of 40 CD74HC595DW

HC595M

SOIC − DW

Reel of 2000 CD74HC595DWR

HC595M

Tube of 40 CD74HC595M

−55°C to 125°C

SOIC − M

Reel of 2500 CD74HC595M96

HC595M

−55 C to 125 C

SOIC − M

Reel of 250 CD74HC595MT

HC595M

SOP − NS Reel of 2000 CD74HC595NSR HC595M

SSOP − SM

Tube of 80 CD74HC595SM

HJ595

SSOP − SM

Reel of 2000 CD74HC595SM96

HJ595

†

Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

DW, E, M, NS, OR SM PACKAGE

(TOP VIEW)

GND

SER

RCLK

SRCLK

SRCLR

H′

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Summary of content (23 pages)

PAGE 1
D 8-Bit Serial-In, Parallel-Out Shift D Wide Operating Voltage Range of 2 V to 6 V D High-Current 3-State Outputs Can Drive Up D D D D D SCHS353 − JANUARY 2004 DW, E, M, NS, OR SM PACKAGE (TOP VIEW) QB QC QD QE QF QG QH GND To 15 LSTTL Loads Low Power Consumption, 80-µA Max ICC Typical tpd = 14 ns ±6-mA Output Drive at 5 V Low Input Current of 1 µA Max Shift Register Has Direct Clear 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC QA SER OE RCLK
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SCHS353 − JANUARY 2004 FUNCTION TABLE INPUTS 2 SER SRCLK X X X X X X L SRCLR FUNCTION RCLK OE X X H X X L Outputs QA−QH are disabled. Outputs QA−QH are enabled. L X X Shift register is cleared. ↑ H X X First stage of the shift register goes low. Other stages store the data of previous stage, respectively. H ↑ H X X First stage of the shift register goes high. Other stages store the data of previous stage, respectively.
PAGE 3
SCHS353 − JANUARY 2004 logic diagram (positive logic) OE RCLK SRCLR SRCLK SER 13 12 10 11 14 1D C1 R 3R C3 3S 15 2S 2R C2 R 3R C3 3S 1 2S 2R C2 R 3R C3 3S 2 2S 2R C2 R 3R C3 3S 3 2S 2R C2 R 3R C3 3S 4 2S 2R C2 R 3R C3 3S 5 2S 2R C2 R 3R C3 3S 6 2S 2R C2 R 3R C3 3S 7 9 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 QA QB QC QD QE QF QG QH QH′ 3
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SCHS353 − JANUARY 2004 timing diagram SRCLK SER RCLK SRCLR OE ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ ÎÎÎÎÎ QA QB QC QD QE QF QG QH QH’ NOTE: 4 ÎÎÎÎ ÎÎÎÎ implies that the output is in 3-State mode.
PAGE 5
SCHS353 − JANUARY 2004 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
PAGE 6
SCHS353 − JANUARY 2004 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS IOH = −20 µA VOH VI = VIH or VIL QH′, IOH = −4 mA QA−QH, IOH = −6 mA QH′, IOH = −5.2 mA QA−QH, IOH = −7.8 mA IOL = 20 µA VOL VI = VIH or VIL QH′, IOL = 4 mA QA−QH, IOL = 6 mA QH′, IOL = 5.2 mA QA−QH, IOL = 7.8 mA 6 TYP 2V 1.9 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.
PAGE 7
SCHS353 − JANUARY 2004 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC MIN fclock Clock frequency SRCLK or RCLK high or low tw Pulse duration SRCLR low SER before SRCLK↑ SRCLK↑ before RCLK↑† tsu Setup time SRCLR low before RCLK↑ SRCLR high (inactive) before SRCLK↑ th Hold time, SER after SRCLK SRCLK↑ TA = -55°C TO 125°C TA = 25°C MAX MIN MAX TA = -40°C TO 85°C MIN 2V 6 4.2 5 4.
PAGE 8
SCHS353 − JANUARY 2004 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SRCLK QH H′ tpd RCLK tPHL ten tdis SRCLR OE OE QA−QH QH H′ QA−QH QA−QH QA−QH tt QH H′ TA = -55°C TO 125°C TA = 25°C VCC MAX MIN MAX TA = -40°C TO 85°C MIN TYP MIN 2V 6 26 4.2 5 4.
PAGE 9
SCHS353 − JANUARY 2004 operating characteristics, TA = 25°C PARAMETER Cpd Power dissipation capacitance POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TEST CONDITIONS TYP UNIT No load 400 pF 9
PAGE 10
SCHS353 − JANUARY 2004 PARAMETER MEASUREMENT INFORMATION VCC S1 Test Point From Output Under Test PARAMETER RL CL (see Note A) tPZH ten 1 kΩ tPZL tPHZ tdis S2 RL tPLZ tpd or tt 1 kΩ Data Input VCC 50% 10% 50% VCC 0V In-Phase Output 50% 10% tPHL 90% 90% tr tPHL Out-ofPhase Output 90% tf Open Closed Closed Open Open Open VCC th 90% 90% VCC 50% 10% 0 V tf 50% 10% Output Control (Low-Level Enabling) VCC 50% 50% 0V tPZL V
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing CD74HC595DWR SOIC SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 12.0 16.0 Q1 DW 16 2000 330.0 16.4 10.75 10.7 2.7 CD74HC595M96 SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.0 Q1 CD74HC595NSR SO NS 16 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) CD74HC595DWR SOIC DW 16 2000 367.0 367.0 38.0 CD74HC595M96 SOIC D 16 2500 333.2 345.9 28.6 CD74HC595NSR SO NS 16 2000 367.0 367.0 38.0 CD74HC595SM96 SSOP DB 16 2000 367.0 367.0 38.
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MECHANICAL DATA MSSO002E – JANUARY 1995 – REVISED DECEMBER 2001 DB (R-PDSO-G**) PLASTIC SMALL-OUTLINE 28 PINS SHOWN 0,38 0,22 0,65 28 0,15 M 15 0,25 0,09 8,20 7,40 5,60 5,00 Gage Plane 1 14 0,25 A 0°–ā8° 0,95 0,55 Seating Plane 2,00 MAX 0,10 0,05 MIN PINS ** 14 16 20 24 28 30 38 A MAX 6,50 6,50 7,50 8,50 10,50 10,50 12,90 A MIN 5,90 5,90 6,90 7,90 9,90 9,90 12,30 DIM 4040065 /E 12/01 NOTES: A. B. C. D. All linear dimensions are in millimeters.
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